| Options | Description |
|---|---|
| DisableFloorplanning | This option disables the auto-floor-planning phase in the mapper. This option is useful for heavily constrained designs where you want to guide mapping phase by using location constraints. |
| BufferOptLevel[1-9] | These options can be used to improve throughput
by reducing memory bank conflicts. At higher BufferOptLevel, mapper
tries to reduce number of buffers getting mapped into same memory
bank, thereby reducing the probability of bank conflicts affecting
overall performance. Higher BufferOptLevels can increase the size of
the overall mapped region, and in few cases, can fail to find a
solution. The default of BufferOptLevels is BufferOptLevel0. |
| disableSeparateTraceSolve | Default trace behavior forces the AI Engine mapper to keep all PLIOs/GMIOs in the original design location when using the trace debug feature. However, if the original solution did not leave any room for trace GMIOs, no solution will be possible unless the design PLIOs are moved. This option is to be used in this case. |
| Options | Description |
|---|---|
| enableSplitAsBroadcast | This option treats all split nets from a split
node as a single net, with 100% usage broadcasting to multiple
points. This broadcast net does not share resources with any other
packet switched net in the design. This option can be used when
throughput degradation is observed due to interference on packetstream nets after split
node. |
| dmaFIFOsInFreeBankOnly | This option ensures DMA FIFOs are only inserted into memory banks that have no other buffers mapped. This option can be used when memory stalls are observed due to DMA FIFO buffers being accessed at the same time as some other design buffer placed in the same bank. |
| disableSSFifoSharing | Disables the ability of the router to share stream switch FIFOs among two or more terminals of a net. This option should only be used when there are not enough stream switch FIFOs in the device to give each terminal its own individual FIFO(s). |