Design Considerations for Graphs Containing Programmable Logic Kernels - 2020.2 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

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2020.2 English

The AI Engine array is made up of AI Engine tiles and AI Engine array interface tiles on the last row of the array. The types of interface tiles include AI Engine-to-PL and AI Engine-to-NoC.

Knowing the PL interface tile, which interfaces and adapts the signals between the AI Engines and the PL region, is essential to take full advantage of the bandwidth between AI Engines and the PL. The following figure shows an expanded view of a single PL interface tile.

Figure 1. AI Engine-PL Interface Tile
Note: Notice the interface tile supports two different clock domains, AI Engine clock and PL clock, as well as a predefined number of streaming channels available to connect from the AI Engine tile to a specific PL interface tile.