Pipeline View for Single Kernel Debug - 2020.2 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

Document ID
Release Date
2020.2 English

The AI Engine pipeline view in the Vitis IDE allows you to correlate instructions executed in a specific clock cycle with the labels in the microcode/disassembler view. The underlying AI Engine pipeline is exposed in debug mode using the pipeline view. The Vitis IDE only supports pipeline view for graphs containing single kernels.

To enable the pipeline view on graphs with a single kernel, select Generate Profile from the project debug configuration after the project has been built successfully.

Important: If your graph has multiple tiles this view does not appear; however multiple kernels within a single tile is supported.
Figure 1. Debug Screen

Click on Debug to start debugging the application. Note the Pipeline view shows up automatically in the Debugger Console window.

Figure 2. Pipeline View

Run-time statistics of the kernel in the pipeline view are highlighted in the previous figure.

  1. AI Engine kernel cycle count
  2. Program counter
  3. ID = Instruction decode
  4. E1-E7 are the AI Engine execution stages. Almost all operations in the scalar unit are scheduled in E1 stage of the pipeline besides non-linear operations. The vector unit scheduling spans from the ID stage to the E6 stage. Address Generation Units (AGUs) span over two pipeline stages. The address is ready in the E2 stage of the pipeline. For load units, the data will be available in the AI Engine from the memory module in the E7 stage. For the store unit, the data will be sent out from the AI Engine to the memory module in the E5 or E6 stage of the pipeline depending on the type of instruction.