PDM supports two methods to estimate NoC power: Manual Entry and Importing from AMD Vivado™ . Of the two methods, Importing from Vivado is more accurate because it based on the physical locations of the NoC connections whereas the Manual Entry mode relies on PDM to estimate the number of NoC clock buffers and switches used. However, the Manual Entry mode has the advantage of not requiring any design or interaction with Vivado.
Manual Entry
For early power estimation when an Vivado design is not yet available or ready.
- Manually specify the configuration of NoC data paths as described above to get the estimated power.
- Create a DDR interface using the DDRMC Wizard if you are using a hard DDRMC in your design.
Importing from Vivado
If there is an IP integrator design available in Vivado with NoC present as an IP, use this flow for NoC power estimation. In this flow, Vivado generates a file with all the information required for NoC power estimation. The power estimated by this flow is more accurate than the manual entry mode. In this flow, the NoC configuration is populated from the actual NoC design and the number of switches and clock buffers are very close to the numbers used in the design.
- After validating a block design in IP integrator, the NOC_Power.xpe file is generated with all the NoC configurations. For a Vivado project, NOC_Power.xpe is found in the project directory.
- Import NOC_Power.xpe into the PDM tool using Import NoC .xpe button available on top of
NoC/DDRMC page.Note: You can also import NOC_Power.xpe on the Summary page