Creating New Project - 2024.1 English

1. Click New Project on the Getting Started screen and click Next.
2. Enter the project name and project location.

   You can also select the .xpe file generated from Vivado or XPE for the import flow.

   
   
   
3. Clicking Next takes you to the part selection wizard (For UltraScale+, select the Architecture as UltraScale+). Select the temperature grade as commercial or industrial and process as typical or maximum and click Next.
   Tip: If *.xpe import flow is selected, then architecture and device details are populated automatically from *.xpe file.
   
   
   

   For device selection details, refer to Device Selection and Settings.

4. Click Next, and click Finish on the New Project Summary page. Your new project with all the default values are created and ready to use.
5. Following is the summary page view in PDM after the new project is created.
   
   

   Use the page navigator on the left-hand side to move between resource-specific pages and the Summary page.

   On the left panel, there are summary and other blocks page for the device. The Summary page has following sections:

   Part

   This panel is the summary of device selection and process setting for power estimation. After making Part changes, select Apply so changes take effect.

   Tip: For worst-case power estimation, use the maximum process. For Kria, worst case estimation is used for all on-board components except the AMD device.

   Summary

   This read-only table shows the total power estimation, junction temperature (Tj) and margin based on the environment settings.

   Environment

   Either force the Junction temperature to a fixed value or specify the maximum ambient temperature and effective ThetaJA for the thermal solution obtained from thermal simulation.

   Recommended: Worst case junction temperature must be used until ThetaJA is obtained from thermal simulations.

   On-Chip (Static/Dynamic) Power

   The On-chip Power tables displays a summary of block-wise power.

   DFX Usage

   The DFX Usage section determines if the NoC clock gating is enabled or disabled. DFX designs with two or more Reconfigurable Partitions (RP) do not support NoC clock gating. All the NoC clock buffers are on and consume power if a design has more than one RP (Applicable only for Versal devices).

   Estimation Section

   Under the Estimation section on the left panel, navigate to specific pages for device resources where you can enter usage, enable, and toggle rates.

At the bottom of the page is a Project Summary status, which remains visible while viewing all of the PDM pages. This information provides a quick summary of the power, thermal settings, and margins for the design.

Click the Show/Hide button at the bottom right corner to hide this pane as needed.

Figure 1. Project Summary Status