AI Engine-ML is available in Versal AI Edge and a few AI Core series devices. The compute tiles are similar to AI-Engine tiles with additional support for BFloat data type. AIE-ML has additional shared memory tiles for improved performance and data movement.
The maximum total supported memory by memory tile is up to 38 Mb across AI Engine Array, depending on the device. Memory tile memory banks have 512 KB SRAM, arranged in 16 physical banks, each 128-bit wide and 2k words deep. For early estimation, an average number of memory banks that can be used is computed and auto-populated by PDM.
AIE-ML supports import of .xpe file that is generated from Vitis AI Engine ML compiler, which is similar to AI Engine for more accurate usage and read/write rates.
For more information refer to Versal Adaptive SoC AIE-ML Architecture Manual (AM020).
AIE and AIE-ML supports two PDM-only modes:
- DSP
- Use this mode when AIE/AIE-ML is used for applications used for signal processing.
- ML
- Use this mode when AIE/AIE-ML is used for ML based applications.
Note: These are PDM-only modes. Any export from AIE/AIE-ML compiler, and simulation exports will not have this information. DSP is the default mode.