AI Engine-ML (AIE-ML) is available in Versal AI Edge devices and a few AI Core Series devices. The compute tiles are similar to AI Engine tiles with additional support for BFloat data type. AIE-ML has additional shared memory tiles for improved performance and data movement.
The maximum total supported memory by memory tile is up to 38 Mb across AI Engine Array, depending on the device. Memory tile memory banks have 512 KB SRAM, arranged in 16 physical banks, each 128-bit wide and 2k words deep. For early estimation, an average number of memory banks that can be used is computed and auto-populated by PDM.
AIE-ML supports import of .xpe file that is generated from Vitis AI Engine ML compiler, which is similar to AI Engine for more accurate usage and read/write rates.
The Versal AI Edge Series Gen 2 devices have AIE-ML v2. The AIE-ML v2 page is identical to AIE-ML except for two new columns in the Customization table:
- Shim Total Tiles
- Core Enable Rate
For more information refer to Versal Adaptive SoC AIE-ML Architecture Manual (AM020).
AI Engine pages include a column for workload type. This value affects the power estimation based on the application. The two PDM-only supported modes are:
- DSP
- Use this mode when AIE orAIE-ML is used for signal processing applications.
- ML
- Use this mode when AIEorAIE-ML is used for ML based applications. Note: These settings are only used by PDM. Any export from the AIE or AIE-ML compiler or export from AIE or AIE-ML simulation do not have this information. DSP is the default mode.