PL Power Management - 2024.2 English - UG1556

The Power Management page enables early "What-if" power saving analysis like Clock Gating, Frequency Scaling, and Logic Gating. This helps you become aware of some of the Power Management opportunities during the early phase of the design power estimation.

Each clock is represented in the Clock Domain Power table.

Figure 1. Power Management

The following power management techniques can be analyzed in the PDM tool.

1. Clock Gating

   Calculates power savings as if the PL clocks are gated, equivalent to a zero frequency clock for Logic, BRAM, URAM and DSP.

2. Frequency Scaling

   Calculates the power savings when a clock runs at a lower frequency. You need to enter the absolute frequency after scaling , not the scaling factor.

3. % of Logic gated

   Calculates power savings from gating a portion of a clock domain. Enter the percentage of logic that could be clock-gated. This can be set only when clock gating is disabled, because when clock gating is enabled, logic power is 0.

   Note: No other pages are affected by analysis on the Power Management page.

Summary of Savings

You can use this table to determine the total power savings broken down by power management category.

Current Design

Represents total power of the design without any power management

Only Clock Gating

This shows the total design power and power savings only due to clock gating.

Only Frequency scaling

This shows the total design power and power savings only due to frequency scaling of the clocks whichever selected.

Only Logic Gating

This shows total design power and power savings as result of % Logic gated.

Clock Domain Power

This table allows you to select the power management modes based on the clocks.

Potential Savings

This table shows the power savings per clock domain. It has 3 different columns that represent how power is saved per Power Management mode per clock.