Creating Clocks - 2024.2 English - UG1556

Clocks must be created or generated before starting a manual estimation flow. This enables the clocks to be selected in other pages.

The PDM tool has a Create Clock wizard to simplify the creation of clocks. This wizard allows creating internal clocks coming from another block, such as PS or GT as well as external clocks from primary inputs.

Fanout for each clock is calculated from totaling its loads from the other resource pages where it is used. This ensures the clock fanout is accurate and updated with changes in resource totals.

Clock Fanout

The number of synchronous loads driven by this clock. It is automatically updated based the number of resources driven by that clock on other pages including Logic, Block RAM, UltraRAM, DSP, and I/O.

Fanout/Site

Fanout/site column represents the average number of connections of the clock to a physical site in a site such as a CLB, block RAM, or DSP block.

For manual power estimation, it is recommended to leave the value as is. For imported .xpe files, the value is provided by the Vivado tools, and is based on the placed and routed results to improve clock power accuracy. The value ranges from 1 (least efficient, highest power) to 16 (most efficient, lowest power).

Clock Buffer Enable Column

This value allows you to model continuous global clock gating. If you plan to use the clock enable of a global clock buffer (BUFGCE) to disable the clock periodically, enter the percentage of time that the clock enable is active. This percentage, also know as the duty cycle, reduces the clock's dynamic power proportionally.

Slice Clock Enable Column

This value allows you to model continuous local clock gating. If you plan to use the slice clock enables to disable the slice registers periodically, enter the percentage of time that the slice clock enable is active. Similar to Clock Buffer Enable, this percentage reduces the clock's dynamic power proportionally.

For clock gating and frequency scaling, refer to PL Power Management.

If power estimation is required for a MMCM or PLL, you can specify these in the Clock Managers section on the Clock page.

You can configure Clock Managers— MMCMs, XPLLs, and DPLLs, from the clock wizard. PDM automatically creates unique instance names for different clock managers. You can specify the reference clock for clock managers by selecting the previously created clocks. If the reference clock is not explicitly specified, then the current external/internal clock in the clock configuration wizard is used as the reference clock for the given clock manager. The wizard allows selecting three different VCO ranges for clock managers. VCO range is used to identify the optimum D and M values for MMCM/PLLs.

Once the clock is created, it is available in the Clock table and is selectable on the other resource pages such as Logic, DSP, UltraRAM, Block RAM, and I/O to estimate the power of these blocks and the power of the clock network.