Creating Clocks - 2024.1 English

The clocks must be created or generated before starting a manual estimation flow. This enables the clocks to be selected in other pages.

The PDM tool has a Create Clock wizard to simplify the creation of clocks. This wizard allows creating internal clocks coming from another block, such as PS or GT as well as external clocks from primary inputs.

Fill in the details in the Create Clock wizard to create a clock. Select an external or internal clock, from another block, such as the processing subsystem (PS), or a GT recovered clock.

Figure 1. Create Clock Wizard

Figure 2. Clock Wizard

Figure 3. Clock Table

Fanout for each clock is calculated from totaling its loads from the other resource pages where it is used. This ensures the clock fanout is accurate and updated with changes in resource totals.

Clock Fanout

The number of synchronous elements driven by this clock. It is automatically updated in PDM based on number logic resources that are associated with a clock on LOGIC, BRAM, URAM, DSP, IO tabs

Fanout/Site

Fanout/site column in AMD devices represents the average number of connections of the clock to a physical logic in a site such as a CLB, block RAM, or DSP block.

For early power estimation, it is recommended to leave the value as is. For imported .xpe files, the value is provided by the Vivado tools, and is based on the placed and routed results to improve clock power accuracy. The value ranges from 1 (least efficient, highest power) to 16 (most efficient, lowest power). For block RAM and DSP sites, the value should be 1, as there is only one fanout in these sites

Clock Buffer Enable Column

Gates the clock net at its source. The value is the percentage of the time in which the clock buffer is active. Reduce this percentage if you plan on disabling the clock net at the source when this portion of the design is not used. This reduces power.

Slice Clock Enable Column

Gates the clock net at its loads at CLB level. Reduce this percentage if you plan on disabling some of the clock loads with slice level Clock Enable signals. This reduces power.

For clock gating and frequency scaling, refer to PL Power Management.

If power estimation is required for a MMCM or PLL, you can specify these in the Clock Managers section on the Clock page.

You can configure Clock Managers, MMCM, XPLL, DPLL from the clock wizard. PDM automatically creates unique instance names for different clock managers. You can specify the reference clock for clock managers by selecting the previously created clocks. If the reference clock is not explicitly specified, then, the current external/internal clock in the clock configuration wizard is used as the reference clock for the given clock manager. Clock wizard allows selecting three different VCO ranges for clock managers. VCO range is used to identify the optimum D and M values for MMCM/PLLs.

Figure 4. Clock Managers

Once the clock is created, it is available in the Clock table and is selectable on the other resource pages such as Logic, DSP, URAM, block RAM, and I/O to estimate the power of these blocks and the power of the clock network.