The Zynq UltraScale+ RFSoC PS block has two major processing units:
- Cortex-A53 application processing unit (APU)-ARM v8 architecture-based 64-bit quad-core multiprocessing CPU.
- Cortex-R5F real-time processing unit (RPU)-ARM v7 architecture-based 32-bit dual real-time processing unit with dedicated tightly coupled memory (TCM).
The Zynq UltraScale+ RFSoC PS has four high-speed serial I/O (HSSIO) interfaces supporting the following protocols:
- Integrated block for PCI Express® interface- PCIe® base specification version 2.1 compliant.
- SATA 3.1 specification compliant interface.
- USB 3.0 interface-compliant to USB 3.0 specification implementing a 5 Gb/s line rate.
- Serial GMII interface-supports a 1 Gb/s SGMII interface.
The PS and PL can be coupled with multiple interfaces and other signals to effectively integrate user-created hardware accelerators and other functions in the PL logic that are accessible to the processors. They can also access memory resources in the processing system. The PS I/O peripherals, including the static/flash memory interfaces share a multiplexed I/O (MIO) of up to 78 MIO pins. Zynq UltraScale+ RFSoCs can also use the I/O in the PL domain for many of the PS I/O peripherals. This is done through an extended multiplexed I/O interface (EMIO) and boots at power-up or reset.
For additional information on Zynq UltraScale+ RFSoC, see the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) and the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more information about configuration options for the Zynq UltraScale+ RFSoC.