The platform management unit (PMU) within the Zynq UltraScale+ RFSoC signals power domain changes using the PMU output pins for deep-sleep mode. The Zynq UltraScale+ RFSoC PMU GPO pins are connected to inputs of the MSP430 system controller through the TXS0108E level-shifter U37. The RFSoC U1 Bank 501 and MSP430 U38 pin numbers are listed in the following table.
| XCZU49DR (U1) Pin | Net Name | MSP430 U38 | |
|---|---|---|---|
| Pin Name | Pin Number | ||
| E32 | MIO37_PMU_GPO5 | P1_0 | 13 |
| E31 | MIO36_PMU_GPO4 | P1_1 | 14 |
| C33 | MIO35_PMU_GPO3 | P1_2 | 15 |
| D31 | MIO34_PMU_GPO2 | P1_3 | 16 |
| D32 | MIO33_PMU_GPO1 | P1_4 | 17 |
| D34 | MIO32_PMU_GPO0 | P1_5 | 18 |
Through the I2C0 bus U1 PS-side MIO[14:15] pins, the PMU has access to the board power controller PMBus bus (IRPS5401_SDA/SCL) and power monitor PMBus (INA226_PMBUS_SDA/SCL). See Figure 1 for additional details.
Refer the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for details about the PMU interface.
The detailed RFSoC connections for the feature described in this section are documented in the ZCU216 board XDC file, referenced in Xilinx Design Constraints.