[Figure 1, callout 39, 40, and 41]
The ZCU216 evaluation board uses power management ICs (PMIC) and regulators from Infineon Integrated Circuits and MPS to supply the core and auxiliary voltages listed in the following table. Reference schematic 038-05003-01.
| Ref. Des., PMBUS ADDR | Controller or Regulator | Rail Name | Voltage (V) | Max. Current (A) | INA226 Power Monitor | INA226 PMBUS ADDR | Sense Resistor (Ω) | Schem. Page |
|---|---|---|---|---|---|---|---|---|
| PMIC1 U104 (0X40) | IR35215_PWM1/2 | VCCINT | 0.85 | 60 | U65 | 0x40 | R440: 0.0005 | 47 |
| IR35215_PWM1_L2 | VCCINT_AMS | 0.85 | 28 | U61 | 0x49 | R1098: 0.0005 | ||
| PMIC2 U53 (0X44) | IRPS5401_A | VCC1V2 | 1.2 | 6 | U58 | 0x43 | R408: 0.005 | 50 |
| IRPS5401_B | UTIL_1V13 | 1.13 | 500 mA | NA | NA | NA | ||
| IRPS5401_C | VADJ_FMC | 1.8 | 6 | U62 | 0x45 | R382: 0.005 | ||
| IRPS5401_D | Tied to channel C | |||||||
| IRPS5401_LDO | MGT1V8 | 1.8 | 500 mA | U64 | 0x48 | R787: 0.005 | ||
| PMIC3 U55 (0X45) | IRPS5401_A | NC | NA | NA | NA | NA | NA | 52 |
| IRPS5401_B | UTIL_2V5 | 2.5 | 500 mA | NA | NA | NA | ||
| IRPS5401_C | MGT1V2 | 1.2 | 7 | U63 | 0x47 | R400: 0.005 | ||
| IRPS5401_D | Tied to 3C | |||||||
| IRPS5401_LDO | MGTRAVCC | 0.85 | 500 mA | NA | NA | NA | ||
| U127 (0X4B) | IR38164 | VCCINT_IO_BRAM_PS | 0.85 | 18 | U57 | 0x41 | R1099: 0.0005 | 53 |
| U112 (0x43) | IR38164 | MGTAVCC | 0.9 | 4 | U67 | 0x46 | R455: 0.002 | 54 |
| U123 (0x4C) | IR38164 | VCC1V8 | 1.8 | 8 | U60 | 0x42 | R879: 0.002 | 55 |
| U115 | MPM3683-7 | ADC_AVCC | 0.925 | 4 | U75 | 0x4C | R499: 0.005 | 56 |
| U116 | MPM3683-7 | DAC_AVCC | 0.925 | 6 | U77 | 0x4E | R504: 0.005 | 56 |
| U114 | MPM3833C | ADC_AVCCAUX | 1.8 | 2 | U71 | 0x4D | R475: 0.005 | 57 |
| U125 | MPM3833C | DAC_AVCCAUX | 1.8 | 1.5 | U124 | 0x4B | R889: 0.005 | 58 |
| U118 | MPM3833C | DAC_AVCCAUX | 2.5/3.0 | 1.5 | U59 | 0x4A | R869: 0.005 | 58 |
| U111 | IR3889 | UTIL_3V3 | 3.3 | 15 | NA | NA | NA | 60 |
| U126 | IR3889 | UTIL_5V0 | 5 | 10 | NA | NA | NA | 61 |
| U79 | IR3897 | PL_DDR4_C0_VTT | 0.6 | +/- 3.0 | NA | NA | NA | 61 |
| U108 | IR3897 | PL_DDR4_C1_VTT | 0.6 | +/- 3.0 | NA | NA | NA | 61 |
| U80 | IR3897 | PS_DDR4_VTT | 0.6 | +/- 3.0 | NA | NA | NA | 62 |
The FMCP HSPC (J28) VADJ pins and RFSoC U1 banks 66 and 67 VCCO pins are wired to the programmable rail VADJ_FMC. The VADJ_FMC rail is programmed to 1.80V by default.
Documentation describing PMBUS programming for the Infineon power controllers as well as PMIC and voltage regulator data sheets are available on the Infineon Integrated Circuits website.
Non-PMBus ADC and DAC voltage regulator data sheets can be viewed on the MPS website.
The PCB layout and power system design meet the recommended criteria described in the UltraScale Architecture PCB Design User Guide (UG583).
report_power command in the Vivado tools for designs targeting this board. The reported rail
current requirements must not exceed the values listed in the following
table.| Device Rail | Maximum Current (Amps) |
|---|---|
| VCCINT | 60 |
| VCCINT_IO + VCCBRAM + VCC_PSINTLP + VCC_PSINTFP + VCC_PSINTFP_DDR | 18 |
| MGTYVCCAUX + VPS_MGTRAVTT | 0.5 |
| MGTYAVCC | 4 |
| VPS_MGTRAVCC | 0.5 |
| MGTYAVTT + VCC_PSPLL | 7 |
| VCCINT_AMS | 28 |
| VADC_AVCC | 4 |
| VADC_AVCCAUX | 2 |
| VDAC_AVCC | 6 |
| VDAC_AVCCAUX | 1.5 |
| VDAC_AVTT | 1.5 |
| VCCAUX + VCCAUX_IO + VCCO 1.8V + VCCAUX_IO + VCC_PSAUX + VCC_PSDDR_PLL + VCCO_PSIO0_500 + VCCO_PSIO1_501 + VCCO_PSIO2_502 + VCCO_PSIO3_503 + VCCADC + VCC_PSADC | 8 |
| VCCO 1.2V + VCCO_PSDDR_504 | 6 |
| VCCO #V (# corresponds to VADJ programmed voltage) | 6 |
The total device power must remain under 50W. To assist the Vivado tools in reporting when power exceeds this amount, add this XDC constraint:
set_operating_conditions -design_power_budget 50 ;# (50W max power)