Clock Generation

ZCU216 Evaluation Board User Guide (UG1390)

Document ID
UG1390
Release Date
2023-12-07
Revision
1.2 English

The ZCU216 board provides fixed and variable clock sources for the ZU49DR Zynq UltraScale+ RFSoC. The following table lists the source devices for each clock.

Table 1. ZCU216 Board Clock Sources
Clock (Net) Name Frequency Clock Source
Fixed Frequency Clocks
PS_REF_CLK 33.33 MHz U43 SI5341B Clock Generator (0x76)
CLK_100 100 MHz
CLK_125 125 MHz
GTR_REF_CLK_SATA 125 MHz
GTR_REF_CLK_USB3 26 MHz
Programmable Frequency Clocks
USER_SI570_C0 300 MHz (Default) U47 SI570 I2C PROG. OSC. (0x5D)
USER_SI570_C1 300 MHz (Default) U130 SI570 I2C PROG. OSC. (0x5D)
USER_MGT_SI570_CLOCK 156.25 MHz (Default) U48 SI570 I2C PROG. OSC. (0x5D)
USER_SMA_MGT_CLOCK User-Provided Source J6 (P)/J7 (N) SMA CONN.
Various 8A34001 eCPRI Clocks Various U409 8A34001 (0x58)

The following table lists the connections for each clock.

Table 2. Clock Connections to ZU49DR U1
Clock Source Ref. Des. and Pin Net Name I/O Standard ZU49DR (U1) Pin
U43 SI5341B Clock Generator
U43.59 PS_REF_CLK (series R300) 1 U32
U43.45 CLK_125_P LVDS A13
U43.44 CLK_125_N LVDS A12
U43.42 CLK_100_P LVDS G12
U43.41 CLK_100_N LVDS G11
U43.35 GTR_REF_CLK_SATA_P 2 AB34
U43.34 GTR_REF_CLK_SATA_N 2 AB35
U43.31 GTR_REF_CLK_USB3_P 2 AC36
U43.30 GTR_REF_CLK_USB3_N 2 AC37
U47 SI570 I2C Prog. Oscillator DDR4 C0 I/F (300 MHz default)
U47.4 USER_SI570_C0_P LVDS AR20
U47.5 USER_SI570_C0_N LVDS AR19
U130 SI570 I2C Prog. Oscillator DDR4 C1 I/F (300 MHz default)
U130.4 USER_SI570_C1_P LVDS G17
U130.5 USER_SI570_C1_N LVDS F17
U49 SI570 I2C Prog. Oscillator (156.250 MHz default)
U48.4 USER_MGT_SI570_CLOCK_P 2 H34
U48.5 USER_MGT_SI570_CLOCK_N 2 H35
J79 (P)/J80 (N) SMA Connectors
J6 USER_SMA_MGT_CLOCK_P 2 M34
J7 USER_SMA_MGT_CLOCK_N 2 M35
U409 8A34001 eCPRI Clock
U409.A9 (Q1) 8A34001_Q1_OUT_P 2 Y39
U409.B9 (Q1) 8A34001_Q1_OUT_N 2 Y40
U409.A11 (Q2) 8A34001_Q2_OUT_P LVDS AT23
U409.B11 (Q2) 8A34001_Q2_OUT_N LVDS AT24
U409.A12 (Q3) 8A34001_Q3_OUT_P LVDS H30
U409.B12 (Q3) 8A34001_Q3_OUT_N LVDS G30
U409.M8 (Q7) 8A34001_Q7_OUT_P 2 T34
U409.L8 (Q7) 8A34001_Q7_OUT_N 2 T35
U409.A6 (Q8) 8A34001_Q8_OUT_P LVDS J21
U409.B6 (Q8) 8A34001_Q8_OUT_N LVDS H21
U409.M6 (Q11) 8A34001_Q11_OUT_P 2 Y34
U409.L6 (Q11) 8A34001_Q11_OUT_N 2 Y35
  1. U1 ZU49DR Bank 503 supports LVCMOS18 level inputs.
  2. Series capacitor coupled, U1 MGT (I/O standards do not apply).
  3. Series capacitor coupled.