Board Features

The ZCU216 evaluation board features are listed here. Detailed information for each feature is provided in Board Component Descriptions.

• XCZU49DR-2, FFVF1760 package
• Form factor: See Board Specifications
• Configuration from:
  • Dual QSPI
  • Micro-SD card
  • USB-to-JTAG Bridge
  • PC4 2x7 2 mm JTAG pod flat cable header
• Clocks
  • GTR_REF_CLK_USB3 26 MHz
  • GTR_REF_CLK_SATA 125 MHz
  • CLK104 (various frequencies):
    • CLK104_PL_CLK
    • CLK104_PL_SYSREF
    • CLK104_AMS_SYSREF
    • CLK104_DDR_PLY_CAP_SYNC
    • CLK104_ADC_REFCLK
    • CLK104_DAC_REFCLK
  • 8A34001 1588 eCPRI (various frequencies):
    • 8A34001_Q1_OUT
    • 8A34001_Q2_OUT
    • 8A34001_Q3_OUT
    • 8A34001_Q7_OUT
    • 8A34001_Q8_OUT
    • 8A34001_Q11_OUT
  • CLK_100 100 MHz
  • CLK_125 125 MHz
  • PS_REF_CLK 33.33 MHz
  • USER_MGT_SI570 (default 156.25 MHz)
  • USER_SI570_C0 (default 300 MHz)
  • USER_SI570_C1 (default 300 MHz)
  • ADC_CLK_225 (direct connect SMAs)
  • DAC_CLK_229 (direct connect SMAs)
  • USER_MGT_SMA_CLK (series capacitor connected SMAs)
• PS DDR4 4 GB 64-bit SODIMM
• PL DDR4 C0 I/F 2 GB 32-bit Component (4x8-bit)
• PL DDR4 C1 I/F 2 GB 32-bit Component (4x8-bit)
• PS GTR (Bank505) assignment
  • USB3 (1 GTR)
  • SATA w/M2 Connector (1 GTR)
  • 2 GTR not used
• PL GTY assignment (4 Quads, 16 total GTY)
  • zSFP+ (4 GTY, 2 on quad GTY128 and 2 on quad GTY129)
  • 8A34001 (1 GTY, quad GTY128)
  • Carlisle CoreHC2 J128 (1 GTY, quad GTY129)
  • FMCP HSCP DP (4 GTY, bank GTY130)
  • FMCP HSCP DP (4 GTY, bank GTY131)
  • 1 GTY not used (quad GTY128)
  • 1 GTY not used (quad GTY129)
• PL FMCP HSCP (FMC+) Connectivity - Full LA[00:33] Bus
• PS MIO Connectivity
  • PS MIO[0:5, 7:12]: Dual QSPI
  • PS MIO[13]: PS_GPIO2
  • PS MIO[14:17]: 2 channels of I2C
  • PS MIO[18:19]: UART0 (1 of 3 FT4232 UART channels)
  • PS MIO[22:23]: PS_PB, PS_LED I/F
  • PS MIO[26]: PMU
  • PS MIO[32:37]: PMU_GPO[0:5]
  • PS MIO[38]: PS_GPIO1
  • PS MIO[40:42, 45:51]: SD I/F
  • PS MIO[52:63]: USB3.0
  • PS MIO[64:77]: Ethernet RGMII
• PL I/O Connections:
  • PL User DIP switch (8-position)
  • PL User pushbuttons (5, Geographic N, S, E, W, C)
  • PL CPU reset pushbutton
  • PL User RGB LEDs (24 total, 8 each R, G, B)
  • PL PMOD0/1 (2 R.A. 2x6 Receptacles)
• Security—PSBATT button battery backup
• SYSMON Header
• Operational Switches (Power on/off, PS_PROG_B, Boot mode DIP switch)
• Operational Status LEDs (INIT, DONE, PS STATUS, PGOOD)
• Power Management
• System Controller (MSP430)

The ZCU216 provides designers a rapid prototyping platform that uses the XCZU49DR-2FFVF1760 device. The ZU49DR contains many useful processor system (PS) hard block peripherals exposed through the multi-use I/O (MIO) interface and a variety of FPGA programmable logic. The following table lists a brief summary of the resources available within the ZU49DR. A feature set overview, description, and ordering information is provided in the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889).