The PS-side GTR transceiver Bank 505 supports USB (3.0) and SATA, with two channels not used.
Bank 505 USB0 lane 2 supports the USB0 (USB3.0) interface documented in the USB 3.0 Transceiver and USB 2.0 ULPI PHY section. The PS-Side GTR transceiver is used to provide USB 3.0 Host-Only connectivity.
Bank 505 SATA lane 3 supports SATA connector U36 shown in Figure 1.
Bank 505 reference clocks are connected to the U43 SI5341B clock generator as detailed in SI5341B 10 Independent Output Any-Frequency Clock Generator U43.
The detailed RFSoC connections for the feature described in this section are documented in the ZCU216 board XDC file, referenced in Xilinx Design Constraints.