The following table shows the relationship between the fields in the Vivado® IDE and the user parameters (which can be viewed in the Tcl Console).
Vivado IDE Parameter/Value 1 | User Parameter/Value | Default Value | Description |
---|---|---|---|
C_MAX_NUM_CHANNELS_MM2S | 2,4,6,8 | 2 | Maximum number of channels supported by the system (MM2S) |
C_MAX_NUM_CHANNELS_S2MM | 2,4,6,8 | 2 | Maximum number of channels supported by the system (S2MM) |
C_INCLUDE_S2MM | 0,1 | 1 |
1: Include S2MM 0: Do not include |
C_INCLUDE_MM2S | 0,1 | 1 |
1: Include MM2S 0: Do not include |
C_S2MM_DATAFORMAT | 0,1,2 | 1 |
0: AES to AES 1: AES to PCM 2: PCM to PCM |
C_MM2S_DATAFORMAT | 0,1,2,3 | 3 |
0: AES to AES 1: AES to PCM 2: PCM to PCM 3: PCM to AES |
C_PACKING_MODE_MM2S | 0,1 | 0 |
0: Interleaved mode 1: Non-Interleaved mode |
C_PACKING_MODE_S2MM | 0,1 | 0 |
0: Interleaved mode 1: Non-Interleaved mode |
C_S2MM_ASYNC_CLOCK | 0,1 | 1 |
ASYNC_CLK parameter of S2MM logic 0: s_axi_lite_aclk and s_axis_s2mm_aclk must be synchronous 1: Clocks can be asynchronous |
C_MM2S_ASYNC_CLOCK | 0,1 | 1 |
ASYNC_CLK parameter of S2MM logic 0: s_axi_lite_aclk and m_axis_mm2s_aclk must be synchronous 1: Clocks can be asynchronous |
|
Note:
- In case of PCM input on AXIS, the valid data should be driven on the applicable LSB bits.
- In case of PCM output on AXIS, the valid data would be driven on applicable LSB bits.
- Width of AXIS data is always 32.