| LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 |
UltraScale+™ UltraScale™ Zynq® UltraScale+™ MPSoC 7 series |
| Supported User Interfaces | AXI4, AXI4-Lite, AXI4-Stream |
| Resources | Performance and Resource Use web page |
| Provided with Core | |
| Design Files | Register Transfer Level (RTL) |
| Example Design | Verilog |
| Test Bench | Verilog |
| Constraints File | Xilinx Constraints File |
| Simulation Model | Not Provided |
| Supported S/W Driver 2 | Standalone and Linux |
| Tested Design Flows 3 | |
| Design Entry | Vivado® Design Suite |
| Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
| Synthesis | Vivado® synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54489 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Xilinx Support web page | |
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