AXI4-Lite Interface Signals |
s_axi_lite_aclk |
Clock |
I |
AXI4-Lite clock for register interface |
s_axi_lite_aresetn |
Reset |
I |
AXI4-Lite reset synchronous to s_axi_lite_aclk |
s_axi_lite_* |
AXI4-Lite
|
- |
AXI4-Lite interface ports for register programming |
S2MM Interface |
s_axis_s2mm_aclk |
Clock |
I |
Clock for AXI4 and stream interfaces of S2MM |
s_axis_s2mm_aresetn |
Reset |
I |
Synchronous reset for s2mm_aclk |
s_axis_s2mm_* |
AXI4-Stream
1
|
- |
Audio AXI4 Streaming input
for S2MM data
1
|
m_axi_s2mm_* |
AXI4 MM |
- |
AXI4 MM interface ports to write data to memory in
S2MM |
Irq_s2mm |
Signal |
O |
S2MM Interrupt signal to indicate period transmission and error
conditions |
MM2S Interface |
m_axis_mm2s_aclk |
Clock |
I |
Clock for AXI4 memory mapped and stream interfaces of
MM2S |
m_axis_mm2s_aresetn |
Reset |
I |
Synchronous reset for mm2s_aclk |
aud_mclk |
Clock |
I |
Audio Master clock for streaming MM2S data at sampling rate |
aud_mreset |
Reset |
I |
Active-High Reset corresponding to aud_mclk |
m_axi_mm2s_* |
AXI4 MM |
- |
AXI4 MM interface ports to read data from memory in
MM2S |
m_axis_mm2s_* |
AXI4-Stream
1
|
- |
AXI4-Stream output in MM2S |
Irq_mm2s |
Signal |
O |
MM2S Interrupt signal to indicate period transmission and error
conditions |
- The streaming interface corresponds to the
AXI4-Stream Audio Interface. It consists of
TDATA, TID, TREADY, and TVALID signals. More details on the interface can be
found in
HDMI 1.4/2.0 Transmitter Subsystem Product
Guide (PG235).
|