| 31 |
0x0 |
R/W1C |
IOC_Irq: Interrupt on Complete.
When set to 1, an interrupt event was generated on the completion of transferring
one period size of data. |
| 30 |
0x0 |
R/W1C |
Err_Irq: Interrupt on Error. When
set to 1, indicates an interrupt event was generated on error. If the corresponding
bit in MM2S_DMACR is enabled (Err_IrqEn = 1), an interrupt out is generated from the
IP. Writing a 1 to this bit clears it. |
| 29:19 |
- |
- |
Reserved |
| 18 |
0x0 |
RO |
MM2S Decode Error: DMA Decode
Error. This error occurs if the address request points to an invalid address. After
it has been set, it is only cleared with a reset.
- 0 = No DMA Decode Errors
- 1 = DMA Decode Error detected
|
| 17 |
0x0 |
RO |
MM2S Slave Error: DMA Slave Error.
This error occurs if the slave read from the Memory Map interface issues a Slave
Error. After it has been set, it is only cleared with a reset.
- 0 = No DMA Slave Errors
- 1 = DMA Slave Error detected
|
| 16:1 |
- |
- |
Reserved |
| 0 |
0x1 |
RO |
Halt in process: DMA Channel Halt in process indication. Asserted
when DMA Run Stop bit goes from 1 to 0 till all the transactions are gracefully
completed.
- 1 = Halting in process
- 0 = Either running state or DMA operations have stopped
|