Each clock in the system has an associated reset synchronous to that clock.
| Clock | Synchronous Reset To | Description |
|---|---|---|
| s_axi_lite_aresetn | active-Low to s_axi_lite_aclk | This reset resets the entire core when active. |
| s_axis_s2mm_aresetn | active-Low to s_axis_s2mm_aclk | Resets the S2MM logic apart from AXI4-Lite register interface. |
| m_axis_mm2s_aresetn | active-Low to m_axis_mm2s_aclk | Resets the MM2S logic apart from AXI4-Lite register interface. |
| aud_mreset | active-Low to Audio Master clock | Resets the sampling frequency counter. This when in reset state, does not generate AXI4-Stream out in MM2S. |
These are all hard resets to the core. Apart from these, there is also a soft reset feature for the core independently for S2MM and MM2S. It gracefully completes the AXI4 Memory Map transactions and ends AXI4-Stream transactions abruptly.