S2MM Status Register Control Register (0x14) - 1.0 English

Audio Formatter LogiCORE IP Product Guide (PG330)

Document ID
PG330
Release Date
2020-07-08
Version
1.0 English
Bit Default Value Access Type Description
31 0x0 W1C IOC_Irq: Interrupt on complete (IOC). Set with each period size of data transferred.
  • 0 = No IOC Interrupt
  • 1 = IOC Interrupt detected.
Writing a 1 to this bit clears it.
30 0x0 W1C Err_Irq: Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit in S2MM_DMACR is enabled (Err_IrqEn = 1), an interrupt out is generated from the IP. Writing a 1 to this bit clears it.
29 0x0 R/C Channel status detected: Indication whenever the channel status bits are updated in the registers 0x2C to 0x40. This bit is cleared on reading.
28:20 - - Reserved
19 0x0 RO Timeout_Error: Error when there is no input audio stream till counter hits timeout value. The core must be reset to ensure proper functionality.
  • 0 = No Timeout
  • 1 = Input timeout
18 0x0 RO S2MM Decode Error: This error occurs if the address request points to an invalid address. This bit is cleared only with a hard or soft reset to S2MM core.
  • 0 = No DMA Decode Errors
  • 1 = DMA Decode Error detected
17 0x0 RO S2MM Slave Error: DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This bit is cleared only with a hard or soft reset to S2MM core.
  • 0 = No DMA Slave Errors.
  • 1 = DMA Slave Error detected.
16:1 - - Reserved
0 0x0 RO Halt in process: S2MM Channel Halt in process indication. Asserted when DMA Run Stop bit goes from 1 to 0 till all the transactions are gracefully completed.
  • 1 = Halting in process
  • 0 = Either running state or DMA operations have stopped