The following table specifies the offset address, register name, and
accessibility of each firmware addressable registers within the UHD-SDI Audio (Embed). User
access to each register is from an offset to the base address.
Note: AES Channel Status
Registers (0x48 to 0x5C) are only valid when GUI option Extract AES Channel
Status is enabled.
Note: SDI Audio Status Registers (0x40, 0x60, 0x70,
and 0x80) are only valid when GUI option Extract SDI Audio Status
is enabled.
| Offset | Name | Description |
|---|---|---|
| 0x00 | Module Control | Register to enable the embedding of audio on to SDI stream. |
| 0x04 | Soft Reset Register | Register to issue soft reset to the core. |
| 0x08 | Core Version Register | Status register conveying the core version |
| 0x0C | Interrupt Enable Register | Register to enable different interrupts |
| 0x10 | Interrupt Status Register | Status register conveying the status of different interrupts |
| 0x14 | Video Control Register | Register to indicate video properties |
| 0x18 | Audio Control Register | Register to indicate audio properties |
| 0x20 | Channel Valid Register | Register to indicate valid channels |
| 0x30 | Channel Mute Register | Register to indicate mute channels |
| 0x40 | Active Group Status Register | Status register conveying the audio groups that are detected on the incoming SDI stream |
| 0x48 | Channel Status Register 1 | Status register conveying the bits [31:0] of AES channel status |
| 0x4C | Channel Status Register 2 | Status register conveying the bits [63:32] of AES channel status |
| 0x50 | Channel Status Register 3 | Status register conveying the bits [95:64] of AES channel status |
| 0x54 | Channel Status Register 4 | Status register conveying the bits [127:96] of AES channel status |
| 0x58 | Channel Status Register 5 |
Status register conveying the bits [159:128] of AES channel status |
| 0x5C | Channel Status Register 6 | Status register conveying the bits [191:160] of AES channel status |
| 0x60 | Active Channel Status Register | Status register conveying the active channel information decoded from audio control packet |
| 0x70 | Sample Rate Status Register | Status register conveying the sample rate information decoded from audio control packet |
| 0x80 | Asynchronous Channel Pair Status Registers | Status register conveying the async channel pair (ASX) information decoded from audio control packet |
| 0xFC | GUI Parameters Status register | Status register conveying the values of the GUI parameters selected during core generation |
| Others | Reserved | Reserved |