|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
adaptive SoC,
AMD UltraScale+™
Families, AMD Zynq™
UltraScale+™ MPSoC, AMD Kintex™
UltraScale™
, AMD Virtex™
UltraScale™
, 7 series,
2
AMD Zynq™ 7000 SoC
|
| Supported User Interfaces |
AXI4-Stream, AXI4-Lite, and Native SDI |
| Resources |
Performance and Resource Use web
page
|
| Provided with
Core
|
| Design Files |
Register Transfer Lever (RTL) |
| Example Design |
Verilog |
| Test Bench |
Not Provided |
| Constraints File |
XDC |
| Simulation Model |
Not Provided |
| Supported S/W Driver
2
|
Standalone and Linux |
| Tested Design Flows
3
|
| Design Entry |
Vivado Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 70290. |
| All Vivado IP Change
Logs |
Master Vivado IP Change Logs:
72775
|
|
Support web
page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog.
-
AMD Artix™ 7 device is not
supported.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|