UHD SDI Audio LogiCORE IP Product Guide (PG309) - 2.0 English

Document ID: PG309
Release Date: 2024-05-30
Version: 2.0 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Core Overview
Applications
Unsupported Features
Licensing and Ordering
Product Specification
AES3 Data Format
AXI4-Stream Audio Interface
AXI4-Lite Slave
AXI4-Stream Slave
Channel Padding Logic
Audio Multiplexer
SDI Audio Status Extract
Audio De-Multiplexer
Clock Phase Logic
AXI4-Stream Master
AES Channel Status Extract
Standards
Performance
Maximum Frequencies
Resource Use
Port Descriptions
UHD-SDI Audio (Embed) Input/Output (I/O) Signals
Configuration Interface [AXI4-Lite Interface Enabled]
Configuration Interface [AXI4-Lite Interface Disabled]
AXI4-Stream Slave Interface [Audio Input]
Reset Output Interface
SDI Input Interface
SDI Output Interface
Interrupt Interface [AXI4-Lite Interface Enabled]
UHD-SDI Audio (Extract) Input/Output (I/O) Signals
Configuration Interface [AXI4-Lite Interface Enabled]
Configuration Interface [AXI4-Lite Interface Disabled]
SDI Input Interface
AXI4-Stream Master Interface [Audio Output]
Reset Output Interface
Interrupt Interface [AXI4-Lite Interface Enabled]
Recovered Clock Interface
Register Space
UHD-SDI Audio (Embed) Register Space
Module Control Register (0x00)
Soft Reset Register (0x04)
Core Version Register (0x08)
Interrupt Enable Register (0x0C)
Interrupt Status Register (0x10)
Video Control Register (0x14)
Audio Control Register (0x18)
Channel Valid Register (0x20)
Channel Mute Register (0x30)
Active Group Status Register (0x40)
Channel Status Register 1 (0x48)
Channel Status Register 2 (0x4C)
Channel Status Register 3 (0x50)
Channel Status Register 4 (0x54)
Channel Status Register 5 (0x58)
Channel Status Register 6 (0x5C)
Active Channel Status Register (0x60)
Sample Rate Status Register (0x70)
Async Channel Pair Status Register (0x80)
GUI Parameters (0xFC)
UHD-SDI Audio (Extract) Register Space
Module Control Register (0x00)
Soft Reset Register (0x04)
Core Version Register (0x08)
Interrupt Enable Register (0x0C)
Interrupt Status Register (0x10)
Audio Control Register (0x18)
Channel Valid Register (0x20)
Channel Mute Register (0x30)
Active Group Status Register (0x40)
RX Sample FIFO Overflow Status Register (0x44)
Channel Status Register 1 (0x48)
Channel Status Register 2 (0x4C)
Channel Status Register 3 (0x50)
Channel Status Register 4 (0x54)
Channel Status Register 5 (0x58)
Channel Status Register 6 (0x5C)
Active Channel Status Register (0x60)
Sample Rate Status Register (0x70)
Async Channel Pair Status Register (0x80)
GUI Parameters (0xFC)
Designing with the Core
Clocking
Resets
Programming Sequence
Design Flow Steps
Customizing and Generating the Core
Configuration for Audio Embed Function
Configuration for Audio Extract Function
User Parameters
Output Generation
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Verification, Compliance, and Interoperability
Hardware Testing
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the UHD SDI Audio Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Hardware Debugging
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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