Interrupt Enable Register (0x0C) - 2.0 English

UHD SDI Audio LogiCORE IP Product Guide (PG309)
Document ID
PG309
Release Date
2024-05-30
Version
2.0 English
Table 1. Interrupt Enable Register (0x0C) - UHD-SDI Audio (Extract)
Bit Field Name Access Type Default Value Description
31:18 N/A reserved 0 Reserved
17 R/W aes_cs_change 0 This bit when set to 1, generates an interrupt when AES channel status value decoded is different from its previous value
16 R/W aes_cs_update 0 This bit when set to 1, generates an interrupt when AES channel status value is updated to the registers (0x48 to 0x5C)
15:13 N/A reserved 0 Reserved
12 R/W asx_change 0 This bit when set to 1, generates an interrupt when ASX value decoded is different from its previous value
11 R/W smpl_rate_change 0 This bit when set to 1, generates an interrupt when sample rate value decoded is different from its previous value
10 R/W act_chan_chang 0 This bit when set to 1, generates an interrupt when active channel value decoded is different from its previous value
9 R/W act_group_change 0 This bit when set to 1, generates an interrupt when active group value decoded is different from its previous value
8 R/W aud_stat_update 0 This bit when set to 1, generates an interrupt when active group (0x40), active channel (0x60), sample rate (0x70) and asx (0x80) registers are updated
7:0 N/A reserved 0 Reserved