| Bit | Field Name | Access Type | Default Value | Description |
|---|---|---|---|---|
| 31:18 | Reserved | N/A | 0 | Reserved |
| 17 | aes_cs_change | RW1C | 0 | This bit when read as 1, indicates that AES channel status value decoded is different from its previous value |
| 16 | aes_cs_update | RW1C | 0 | This bit when read as 1, indicates that AES channel status registers (0x48 to 0x5C) are updated |
| 15:13 | Reserved | RW1C | 0 | Reserved |
| 12 | asx_change | RW1C | 0 | This bit when read as 1, indicates that ASX value decoded is different from its previous value |
| 11 | smpl_rate_change | RW1C | 0 | This bit when read as 1, indicates that sample rate value decoded is different from its previous value |
| 10 | act_chan_change | RW1C | 0 | This bit when read as 1, indicates that active channel value decoded is different from its previous value |
| 9 | act_group_change | RW1C | 0 | This bit when read as 1, indicates that active group value decoded is different from its previous value |
| 8 | aud_stat_update | RW1C | 0 | This bit when read as 1, indicates that active group (0x40), active channel (0x60), sample rate (0x70) and asx (0x80) registers are updated |
| 7:4 | Reserved | N/A | 0 | Reserved |
| 3 | vid_prop_change | R/W | 0 | This bit when read as 1, indicates that change in incoming video properties is detected |
| 2 | rs_fifo_overflow | R/W | 0 | This bit when read as 1, indicates that receive sample FIFO is overflowing |
| 1 | checksum_error | R/W | 0 | This bit when read as 1, indicates that checksum error is detected |
| 0 | parity_error | R/W | 0 |
This bit when read as 1, indicates that parity error is detected |