Required Constraints
The period of the sdi_embed_clk and sdi_extract_clk must be constrained depending on the maximum line rate to be supported. Also, the period of the AXI4-Stream and AXI4-Lite clocks must be constrained based on the system design.
Device, Package, and Speed Grade Selections
For 7 series devices, -3 speed grade parts are required to support 12G-SDI. Not all packages support 12G-SDI line rates. The MGTAVCC voltage rail must be set to 1.05V if 12G-SDI operation is required. This voltage level also supports the other SDI lines rates. If the maximum line rate is 6G-SDI or slower, then -1 speed grade devices are sufficient and the MGTAVCC voltage rail can be set to the normal value of 1.00V.
UltraScale/UltraScale+ GTH/GTY transceivers support operation at all SDI rates up to and including 12G-SDI in -1 speed grade devices.
Clock Frequencies
The source of the sdi_embed_clk is usually the serial transceiver's TXOUTCLK. The source of the sdi_extract_clk is usually the serial transceiver’s RXOUTCLK. The exact constraints to be used on these clocks depends on the hierarchical structure of the design, but they would be similar to the constraints shown below with an application specific path to the TXOUTCLK and RXOUTCLK pins of the serial transceiver.
Applications that support 12G-SDI operation must constrain the frequency of the UHD-SDI Audio IP core's sdi_embed_clk and sdi_extract_clk to 297 MHz.
create_clock -period 3.367 -name tx0_outclk -waveform {0.000 1.683} [get_pins SDI/GTX/gtxe2_i/TXOUTCLK]
create_clock -period 3.367 -name rx0_outclk -waveform {0.000 1.683} [get_pins SDI/GTX/gtxe2_i/RXOUTCLK]
When the maximum line rate is 6G-SDI or slower, the maximum clock frequency of sdi_embed_clk and sdi_extract_clk is 148.5 MHz and the constraints below would be appropriate:
create_clock -period 6.734 -name tx0_outclk -waveform {0.000 3.367} [get_pins SDI/GTX/gtxe2_i/TXOUTCLK]
create_clock -period 6.734 -name rx0_outclk -waveform {0.000 3.367} [get_pins SDI/GTX/gtxe2_i/RXOUTCLK]
Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.