Clocking - 3.1 English

This section describes the link clock (tx_lnk_clk) and the video clock (tx_vid_clk_stream1). The AXI4-Stream to Video Bridge can handle asynchronous clocking. The value is based on the Consumer Electronics Association (CEA)/VESA Display Monitor Timing (DMT) standard for given video resolutions.

The tx_lnk_clk is a link clock input to the DisplayPort 1.4 TX Subsystem generated by the Video PHY (GT). The frequency of tx_lnk_clk is <line_rate> /20 MHz for 16-bit interface.

The hdcp_ext_clk input can be driven from external MMCM or BUFGCDIV where it has a frequency requirement of hdcp_ext_clk = tx_lnk_clk/2 MHz.

In both native and AXI4-Stream modes, TX video clock value is based on the Consumer Electronics Association (CEA)/VESA Display Monitor Timing (DMT) standard for given video resolutions.

The core uses the following clock domains:

lnk_clk

The txoutclk from the Video PHY is connected to the TX subsystem link clock. Most of the core operates in the link clock domain. This domain is based on the lnk_clk_p/n reference clock for the transceivers. The link rate switching is handled by a DRP state machine in the core PHY later. When the lanes are running at 2.7 Gbps, lnk_clk operates at 135 MHz . When the lanes are running at 1.62 Gbps, lnk_clk operates at 81 MHz . When the lanes are running at 5.4 Gbps, lnk_clk operates at 270 MHz . When the lanes are running at 8.1 Gbps, lnk_clk operates at 202.5 MHz .

Note: lnk_clk = link_rate/20, when the GT data width is 16-bit .

vid_clk

It is the primary user interface clock based on the DisplayPort Standard. The video clock can be derived from the link clock using mvid and nvid. Also, vid_clk should be at least [(Vtotal x Htotal x frames per second)/pixels per clock]. Here, Pixels per clock for a given video stream is equal to the value programmed in the AXI4-Lite register corresponding to that video stream, at one of the address locations 0x1B8, 0x538, 0x588, or 0x5D8.For YCbCr420 colorimetry, the vid_clk frequency will be half the actual vid_clk.

Important: DisplayPort TX core's input pixel data (on its native interface) is fed with respect to the pixel clock (vid_clk). Hence, if the incoming data does not exactly match the pixel clock rate, the Display Port TX core might overflow/underflow.

For example, if the pixel data is received from a DisplayPort RX subsystem core, the pixel rate is variable (that is, the rate can have a slight deviation from the exact pixel rate), but the corresponding pixel clock rate for that resolution is constant. That means, DisplayPort RX Subsystem cannot be directly connected to a DisplayPort TX subsystem without a frame buffer or without a way to adjust the pixel rate (to exactly match the pixel clock rate) into the DisplayPort TX core.

s_axis_aclk_stream<n>

This is a constant clock (typically 300 MHz) whose frequency should be at least the maximum possible frequency of vid_clk. This clock is used to input the AXI4-Stream data to the subsystem.

s_axi_aclk

This is the processor domain. It has been tested to run as fast as 135 MHz. The AUX clock domain is derived from this domain, but requires no additional constraints. In an AMD UltraScale™ FPGA, s_axi_aclk clock is connected to a free-running clock input. gtwiz_reset_clk_freerun_in is required by the reset controller helper block to reset the transceiver primitives. A new GUI parameter is added for AXI_Frequency, when the DisplayPort IP is targeted to UltraScale FPGA.

aud_clk

This is the audio interface clock. The frequency is equal to 512 × audio sample rate.

s_axis_audio_ingress_aclk

This clock is used by the source audio streaming interface. It should be = 512 × audio sample rate.

For more information on clocking, see the Video PHY Controller LogiCORE IP Product Guide (PG230).