| Offset | Access Type | Description |
|---|---|---|
| 0x04C | R/W | [31:0] - VERSAL_GT_CTRL. Versal GT controller configuration bits |
| 0x280 | RO |
PHY_STATUS. Provides the current status from the PHY. [31:30] - Unused, read as 0. [29:28] - Transmitter buffer status, lane 3. [27:26] - Unused, read as 0. [25:24] - Transmitter buffer status, lane 2. [23:22] - Unused, read as 0. [21:20] - Transmitter buffer status, lane 1. [19:18] - Unused, read as 0. [17:16] - Transmitter buffer status, lane 0. [15:7] - Unused, read as 0. [6] - FPGA fabric clock PLL locked. [5] - PLL for lanes 2 and 3 locked. [4] - PLL for lanes 0 and 1 locked. [3:2] - Reset done for lanes 2 and 3. [1:0] - Reset done for lanes 0 and 1. |