Training Pattern 2/3/4 Procedure (Symbol Recovery, Interlane Alignment) for 8b/10b Channel Coding Link Rates - 3.1 English

DisplayPort 1.4 TX Subsystem Product Guide (PG299)
Document ID
PG299
Release Date
2024-05-30
Version
3.1 English
  1. Turn off scrambling and set training pattern 2 in the source through direct register writes.

    SCRAMBLING_DISABLE = 0x01 (Not applicable for Training Pattern 4)

    Set training pattern to pattern 2, pattern 3, or pattern 4 based on the Sink DPCD capability

  2. Set proper state for scrambling and set training pattern in the sink DPCD (0x00102 to 0x00106) through the AUX channel.
  3. Wait for AUX read interval configured in TRAINING_AUX_RD_INTERVAL DPCD register (0x0000E) then read status registers for all active lanes (0x00202 to 0x00203) through the AUX channel.
  4. Check the channel equalization, symbol lock, and interlane alignment status bits for all active lanes (0x00204) through the AUX channel.
  5. If any of these bits are not set, check for voltage swing or pre-emphasis level increase requests (0x00206 to 0x00207) and react accordingly.
  6. Run this loop up to five times. If after five iterations this has not succeeded, reduce link speed if at high speed and Return to the instructions for Training Pattern 1. If already at low speed, training fails.
  7. Signal the end of training by enabling scrambling and setting training pattern to 0x00 in the Sink device (0x00102) through the AUX channel.
  8. On the source side, re-enable scrambling and turn off training.
    TRAINING_PATTERN_SET = 0x00
    SCRAMBLING_DISABLE = 0x00