Primarily, arbitration is granted based on the relative priority of the associated SI slot. The ARB_PRIORITY parameter for each SI slot can be set to a static priority value between 0 and 15; higher values have higher priority. In case of a tie:
•SI slot requests are disqualified if the SI slot acceptance limit or the targeted MI issuing limit has been reached. These disqualified requests are ignored by the arbiter.
•When the priority level of all qualified requesting SI slots have level 0, arbitration among them is decided by round-robin.
•When the highest priority value among the requesting SI slots is greater than 0, priority among slots sharing that priority value is based on their slot number; lower slot numbers have higher priority.
Write or Read transactions received at SI slots that have reached their acceptance limit are temporarily disqualified from arbitration so that the Write or Read arbiter, respectively, can continue to grant arbitration to other qualified SI slots, rather than stalling.
Furthermore, transactions that target an MI slot that has reached its issuing limit are also temporarily disqualified from arbitration. Such transaction requests remain disqualified until one cycle after the completion of a prior transaction on the targeted MI slot. (Completion of a write transaction occurs when BVALID and BREADY are both sampled High; completion of a read transaction occurs when RVALID, RREADY and RLAST are sampled High.) During the cycle in which the transaction completes, before the previously-pending requests become qualified, if a new assertion of AWVALID or ARVALID occurs on any other SI slot, it is allowed to be granted arbitration, even ahead of the previously-pending requests, regardless of its relative position in the round-robin queue. The arbiter is vulnerable to this priority inversion only during the one cycle in which a transaction completes on an MI slot that has previously reached its issuing limit. However, if a master device repeatedly asserts its AWVALID/ARVALID during the same cycle as it asserts its BREADY/RREADY in response to a prior transaction completion, it might lead to arbitration starvation on one or more of the previously-requesting SI slots. Any pipeline delay between the master and the crossbar, such as a width converter, will prevent the SI slot from re-requesting arbitration during the same cycle as a prior transaction completion. You can introduce such a pipeline delay, if needed, by simply enabling the register slice for the SI slot in the configuration of the AXI Interconnect.