AXI Crossbar - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

This Figure shows the baseline latency model for the crossbar module.

 

Figure 2-7:      Crossbar Model Baseline Latency

X-Ref Target - Figure 2-7

pg059_x12091.jpg

In This Figure, the baseline latency is as follows:

T_AW = T_AR = 2 cycles of aclk, for the forward propagation of aw/arvalid, provided there are no pending conditions that would inhibit granting arbitration (such as a higher-priority request). Each arbitration also causes 2 bubble cycles, resulting in 3 cycles (minimum) between successive arbitrations by the same SI slot.

T_WC = 1 cycle of aclk.

T_W = 1 cycle of aclk, with no bubble cycles (supports continuous back-to-back data transmission).

T_R = 1 or 2 cycles of aclk, with no bubble cycles (supports continuous back-to-back data transmission). The second latency cycle occurs when there is a re-arbitration (when the requesting MI slot is different than the last granted MI slot) following an idle cycle. While the same MI slot propagates back-to-back data, or while multiple MI slots continuously interleave data, latency through the R-channel arbiter is 1 cycle.

T_B (B-channel latency, not shown) = 1 or 2 cycles of aclk. (Same as for T_R.)