The Width Conversion core performs a downsizer function whenever the data width on the SI side is wider than that on the MI side. During transactions in which the size of the data transfers (according to awsize or arsize) is wider than the data width on the MI side, downsizing is performed and, in the transaction issued to the MI side, the number of data beats is multiplied up accordingly.
•For writes, data serialization occurs on the W-channel between the SI and MI.
•For reads, data merging occurs on the R-channel between the MI and SI.
During merging, the AXI Data Width Converter sets the rresp for each output data beat (on the SI) to the worst-case error condition encountered among the input data beats being merged, according to the following descending precedence order: DECERR, SLVERR, OKAY, EXOKAY.
See Table: AXI Data Width Converter Functional Truth Table and Table: AXI Data Width Converter Transaction Transformation Formulae3 for details on the downsizing transformations for the various configurations and transaction types.When the transfer size of the transaction is equal to or less than the MI side data width, the transaction (address channel values) remains unchanged. Data transfers pass through unchanged except for byte-lane steering. This applies to both writes and reads.
The AXI Data Width Converter core factors up the length of each burst and detects when the resulting burst length would exceed the maximum burst limit (256 data beats for AXI4, 16 for AXI3). In such cases, the AXI Data Width Converter splits the transaction automatically into multiple conforming burst transactions.
•Exclusive Access is not supported through downsizers when burst lengths require splitting. If the awlock or arlock signal indicates an Exclusive Access write or read transaction, and downsizing results in splitting, then the AXI Data Width Converter core changes the lock signal in all output transactions to indicate Normal Access (0).
•When a downsized Write transaction results in splitting, the AXI Data Width Converter core coalesces the multiple Write responses at the MI and issues one Write response on the SI. The core sets the error response code (BRESP) to the worst-case error condition encountered among the multiple input responses, according to the following descending precedence order: DECERR, SLVERR, OKAY (EXOKAY cannot occur in a split transaction).
Downsizing, including transaction splitting, is not restricted by values of the AW/ARCACHE signal (specifically the “Modifiable” bit). Transaction splitting due to downsizing cannot be restricted by CACHE because there is no other alternative for completing the transaction.
The Data Width Converter allows multiple outstanding transactions to be propagated. Transaction characteristics from the AW/AR channel transfers are queued while awaiting corresponding response transfers.
However, due to the possibility of write response and read data re-ordering, transactions issued on the MI side of the Data Width Converter are restricted to a reordering depth of 1 (single ID thread).
As a result, the currently active transaction ID is stored internally and no ID signals are present on the MI. This eliminates the need for downstream IP cores to store and process ID information, saving logic.
Because the Data Width Converter changes the number of transfers on address and data channels between the SI and MI, no user signals are propagated across the core.
The Data Width Converter does not support downsizing directly from 1024 bits to 32. When configuring the AXI Interconnect core, If any SI is 1024 bits, the AXI Crossbar data width of the core must be set to a value greater than 32. If any MI is 32 bits, the AXI Crossbar core data width must be set to a value less than 1024.
When configured for AXI4-Lite protocol, the Data Width Converter provides for downsizing from 64-bit to 32-bit AXI4-Lite transfers. For reads, each SI transaction results in 2 MI transactions when the address is 64-bit-aligned; otherwise, 1 MI transaction for unaligned address. For writes, 64-bit-aligned SI transactions result in 2 MI transactions only when there is at least 1 byte lane (WSTRB) active for each 32-bit word.
You can also instantiate the AXI Data Width Converter core directly in your design (without AXI Interconnect core) along any pathway between a wide AXI master device and a narrower AXI slave.