Master Interface I/O SIgnals - 2.1 English

Mmm_ACLK

Input

REQ

1

Master interface clock input

Mmm_ARESETN

Input

REQ

1

Master interface reset input (active-Low)

Mmm_AXI_AWID

Output

[1–32]

Write Address Channel Transaction ID.

Mmm_AXI_AWADDR

Output

[12–64]

Write Address Channel Address.

Mmm_AXI_AWLEN

Output

AXI4: 8

AXI3: 4

Write Address Channel Burst Length code. (0–255).

Mmm_AXI_AWSIZE

Output

3

Write Address Channel Transfer Size code (0–7).

Mmm_AXI_AWBURST

Output

2

Write Address Channel Burst Type (0–2).

Mmm_AXI_AWLOCK

Output

AXI4: 1

AXI3: 2

Write Address Channel Atomic Access Type
(0, 1).

Mmm_AXI_AWCACHE

Output

4

Write Address Channel Cache Characteristics.

Mmm_AXI_AWPROT

Output

3

Write Address Channel Protection Bits

Mmm_AXI_AWREGION

Output

4

AXI4 Write Address Channel address region index.

Mmm_AXI_AWQOS⁽¹⁾

Output

4

Write Address Channel Quality of Service.

Mmm_AXI_AWUSER

Output

[1–1024]

User-defined AW Channel signals.

Mmm_AXI_AWVALID

Output

1

Write Address Channel Valid.

Mmm_AXI_AWREADY

Input

REQ

1

Write Address Channel Ready.

Mmm_AXI_WID

Output

[1–32]

Write Data Channel Transaction ID for AXI3 slaves

Mmm_AXI_WDATA

Output

[32, 64, 128, 256,
512, 1024]

Write Data Channel Data.

Mmm_AXI_WSTRB

Output

[32, 64, 128, 256,
512, 1024] / 8

Write Data Channel Data Byte Strobes.

Mmm_AXI_WLAST

Output

1

Write Data Channel Last Data Beat.

Mmm_AXI_WUSER

Output

[1–1024]

User-defined W Channel signals.

Mmm_AXI_WVALID

Output

1

Write Data Channel Valid.

Mmm_AXI_WREADY

Input

REQ

1

Write Data Channel Ready.

Mmm_AXI_BID

Input

AXI3, AXI4: REQ

AXI4-Lite: d/c

[1–32]

Write Response Channel Transaction ID.

Mmm_AXI_BRESP

Input

0b00

2

Write Response Channel Response Code (0–3).

Mmm_AXI_BUSER

Input

AXI3, AXI4: 0

AXI4-Lite: d/c

[1–1024]

User-defined B Channel signals.

Mmm_AXI_BVALID

Input

REQ

1

Write Response Channel Valid.

Mmm_AXI_BREADY

Output

1

Write Response Channel Ready.

Mmm_AXI_ARID

Output

[1–32]

Read Address Channel Transaction ID.

Mmm_AXI_ARADDR

Output

[12–64]

Read Address Channel Address.

Mmm_AXI_ARLEN

Output

AXI4: 8

AXI3: 4

Read Address Channel Burst Length code (0–255).

Mmm_AXI_ARSIZE

Output

3

Read Address Channel Transfer Size code (0–7).

Mmm_AXI_ARBURST

Output

2

Read Address Channel Burst Type (0–2).

Mmm_AXI_ARLOCK

Output

AXI4: 1

AXI3: 2

Read Address Channel Atomic Access Type (0,1).

Mmm_AXI_ARCACHE

Output

4

Read Address Channel Cache Characteristics.

Mmm_AXI_ARPROT

Output

3

Read Address Channel Protection Bits.

Mmm_AXI_ARREGION

Output

4

AXI4 Read Address Channel address region index.

Mmm_AXI_ARQOS⁽¹⁾

Output

4

AXI4 Read Address Channel Quality of Service.

Mmm_AXI_ARUSER

Output

[1–1024]

User-defined AR Channel signals.

Mmm_AXI_ARVALID

Output

1

Read Address Channel Valid.

Mmm_AXI_ARREADY

Input

REQ

1

Read Address Channel Ready.

Mmm_AXI_RID

Input

AXI3, AXI4: REQ

AXI4-Lite: d/c

[1–32]

Read Data Channel Transaction ID.

Mmm_AXI_RDATA

Input

REQ

[32, 64, 128, 256, 512, 1024]

Read Data Channel Data.

Mmm_AXI_RRESP

Input

0b00

2

Read Data Channel Response Code (0–3).

Mmm_AXI_RLAST

Input

AXI3, AXI4: REQ

AXI4-Lite: d/c

1

Read Data Channel Last Data Beat.

Mmm_AXI_RUSER

Input

AXI3, AXI4: 0

AXI4-Lite: d/c

[1–1024]

User-defined R Channel signals.

Mmm_AXI_RVALID

Input

REQ

1

Read Data Channel Valid.

Mmm_AXI_RREADY

Output

1

Read Data Channel Ready.

Notes:

1.Although the QOS signals are defined only by the AXI4 protocol specification, this interconnect IP core also propagates QOS signals for any MI slot configured as AXI3.

Port Signal Name

Direction

Default

Width

Description (Range)

ACLK

Input

REQ

1

Crossbar clock input.

ARESETN

Input

REQ

1

Crossbar Reset (active-Low).