Table: AXI Infrastructure Core Master I/O Signals lists the Master Interface signals for the cores.
Signal Name |
Direction |
Default |
Width |
Description (Range) |
---|---|---|---|---|
m_axi_aclk |
Input |
REQ |
1 |
Master interface clock input. AXI Clock Converter and Data Width Converter core only. |
m_axi_aresetn |
Input |
REQ |
1 |
Master interface reset input (active-Low). AXI Clock Converter and Data Width Converter core only. |
m_axi_awid(1) |
Output |
|
ID_WIDTH |
Write Address Channel Transaction ID. |
m_axi_awaddr |
Output |
|
ADDR_WIDTH |
Write Address Channel Address. |
m_axi_awlen |
Output |
|
AXI4: 8 AXI3: 4 |
Write Address Channel Burst Length code. (0–255). |
m_axi_awsize |
Output |
|
3 |
Write Address Channel Transfer Size code (0–7). |
m_axi_awburst |
Output |
|
2 |
Write Address Channel Burst Type (0–2). |
m_axi_awlock |
Output |
|
AXI4: 1 AXI3: 2 |
Write Address Channel Atomic Access Type (0, 1). |
m_axi_awcache |
Output |
|
4 |
Write Address Channel Cache Characteristics. |
m_axi_awprot |
Output |
|
3 |
Write Address Channel Protection Bits |
m_axi_awregion |
Output |
|
4 |
AXI4 Write Address Channel address region index. |
m_axi_awqos(2) |
Output |
|
4 |
Write Address Channel Quality of Service. |
m_axi_awuser(1) |
Output |
|
AWUSER_WIDTH |
User-defined AW Channel signals. |
m_axi_awvalid |
Output |
|
1 |
Write Address Channel Valid. |
m_axi_awready |
Input |
REQ |
1 |
Write Address Channel Ready. |
m_axi_wid(1) |
Output |
|
ID_WIDTH |
Write Data Channel Transaction ID for AXI3 slaves |
m_axi_wdata |
Output |
|
Data Width Converter: M_AXI_DATA_WIDTH; Others: DATA_WIDTH |
Write Data Channel Data. |
m_axi_wstrb |
Output |
|
Data Width Converter: M_AXI_DATA_WIDTH/8; Others: DATA_WIDTH/8 |
Write Data Channel Data Byte Strobes. |
m_axi_wlast |
Output |
|
1 |
Write Data Channel Last Data Beat. |
m_axi_wuser(1) |
Output |
|
WUSER_WIDTH |
User-defined W Channel signals. |
m_axi_wvalid |
Output |
|
1 |
Write Data Channel Valid. |
m_axi_wready |
Input |
REQ |
1 |
Write Data Channel Ready. |
m_axi_bid(1) |
Input |
AXI3, AXI4: REQ AXI4-Lite: d/c |
ID_WIDTH |
Write Response Channel Transaction ID. |
m_axi_bresp |
Input |
0b00 |
2 |
Write Response Channel Response Code (0–3). |
m_axi_buser(1) |
Input |
AXI3, AXI4: 0 AXI4-Lite: d/c |
BUSER_WIDTH |
User-defined B Channel signals. |
m_axi_bvalid |
Input |
REQ |
1 |
Write Response Channel Valid. |
m_axi_bready |
Output |
|
1 |
Write Response Channel Ready. |
m_axi_arid(1) |
Output |
|
ID_WIDTH |
Read Address Channel Transaction ID. |
m_axi_araddr |
Output |
|
ADDR_WIDTH |
Read Address Channel Address. |
m_axi_arlen |
Output |
|
AXI4: 8 AXI3: 4 |
Read Address Channel Burst Length code (0–255). |
m_axi_arsize |
Output |
|
3 |
Read Address Channel Transfer Size code (0–7). |
m_axi_arburst |
Output |
|
2 |
Read Address Channel Burst Type (0–2). |
m_axi_arlock |
Output |
|
AXI4: 1 AXI3: 2 |
Read Address Channel Atomic Access Type (0,1). |
m_axi_arcache |
Output |
|
4 |
Read Address Channel Cache Characteristics. |
m_axi_arprot |
Output |
|
3 |
Read Address Channel Protection Bits. |
m_axi_arregion |
Output |
|
4 |
AXI4 Read Address Channel address region index. |
m_axi_arqos(2) |
Output |
|
4 |
AXI4 Read Address Channel Quality of Service. |
m_axi_aruser(1) |
Output |
|
ARUSER_WIDTH |
User-defined AR Channel signals. |
m_axi_arvalid |
Output |
|
1 |
Read Address Channel Valid. |
m_axi_arready |
Input |
REQ |
1 |
Read Address Channel Ready. |
m_axi_rid(1) |
Input |
AXI3, AXI4: REQ AXI4-Lite: d/c |
ID_WIDTH |
Read Data Channel Transaction ID. |
m_axi_rdata |
Input |
REQ |
Data Width Converter: M_AXI_DATA_WIDTH; Others: DATA_WIDTH |
Read Data Channel Data. |
m_axi_rresp |
Input |
0b00 |
2 |
Read Data Channel Response Code (0–3). |
m_axi_rlast |
Input |
AXI3, AXI4: REQ AXI4-Lite: d/c |
1 |
Read Data Channel Last Data Beat. |
m_axi_ruser(1) |
Input |
AXI3, AXI4: 0 AXI4-Lite: d/c |
RUSER_WIDTH |
User-defined R Channel signals. |
m_axi_rvalid |
Input |
REQ |
1 |
Read Data Channel Valid. |
m_axi_rready |
Output |
|
1 |
Read Data Channel Ready. |
Notes: 1.Signal not present on Data Width Converter core. 2.Although the QOS signals are defined only by the AXI4 protocol specification, this interconnect IP core also propagates QOS signals for any MI slot configured as AXI |