Register Slice Options - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

REG_AW

°Description: Mode of channel register slice

°Format/Range: String (Bypass, Full, Light, SI_Reg, SLR Crossing, SLR TDM Crossing, Multi SLR Crossing)

°Default Value: Light

REG_AR

°Description: Mode of channel register slice

°Format/Range: String (Bypass, Full, Light, SI_Reg, SLR Crossing, SLR TDM Crossing, Multi SLR Crossing)

°Default Value: Light

REG_W

°Description: Mode of channel register slice

°Format/Range: String (Bypass, Full, Light, SI_Reg, SLR Crossing, SLR TDM Crossing, Multi SLR Crossing)

°Default Value: Light if PROTOCOL = AXI4LITE, otherwise Full

REG_R

°Description: Mode of channel register slice

°Format/Range: String (Bypass, Full, Light, SI_Reg, SLR Crossing, SLR TDM Crossing, Multi SLR Crossing)

°Default Value: Light if PROTOCOL = AXI4LITE, otherwise Full

REG_B

°Description: Mode of channel register slice

°Format/Range: String (Bypass, Full, Light, SI_Reg, SLR Crossing, SLR TDM Crossing, Multi SLR Crossing)

°Default Value: Light

For additional operating modes of the register slice core, see AXI Register Slice LogiCORE IP Product Guide (PG373) [Ref 16].