Each SI and each MI of the AXI Interconnect core has its own corresponding ACLK input, as does the underlying Crossbar core. See Clock Conversion for information about capabilities of the Interconnect for performing clock domain crossing.
When the clock source connected to the ACLK input of an SI or MI is the same as the clock connected to the Crossbar (no clock conversion), the SI or MI ACLK input is used to synchronize all AXI Infrastructure cores (such as Data Width Converter or Register Slice), if any, which are instantiated in the SI or MI hemisphere, respectively. When the aclk of a SI is connected to a different source than the Crossbar, a Clock Converter core is instantiated. All Infrastructure cores on the SI (left) side of the Clock Converter, if any, are synchronized by the SI ACLK, while all cores between the Clock Converter and the Crossbar, if any, are synchronized by the Crossbar aclk input. Similarly, when clock conversion is performed in the MI hemisphere, Infrastructure cores on the MI (right) side of the Clock Converter, if any, are synchronized by the MI aclk, while all cores between the Crossbar and the Clock Converter, if any, are synchronized by the Crossbar aclk input.
The clock conversion IP core, including Data Width Converter configured in FIFO Mode, can perform either synchronous or asynchronous clock conversion. When configured for synchronous conversion, it is required that the SI and MI clocks remain edge-aligned at all times.
When using a Clock Wizard IP core to generate the AXI clocks, make sure the actual output clock frequencies maintain an integer-ratio relationship (1:2, 1:3... 1:16), as the actual frequency might differ from the requested frequency for each clock.