• Support for progressive or interlaced video frame sizes up to 16,384 x 16,384
• Direct regeneration of output timing signals with independent timing and polarity inversion
• Automatic detection and generation of horizontal and vertical video timing signals
• Support for multiple combinations of blanking or synchronization signals
• Automatic detection of input video control signal polarities
• Support for detection and generation of horizontal delay of vertical blank/sync
• Programmable output video signal polarities
• Generation of up to 16 additional independent output frame synchronization signals
• Optional AXI4-Lite processor interface
• High number of interrupts and status registers for easy system control and integration
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LogiCORE IP Facts Table |
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Core Specifics |
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AMD Versal™ adaptive SoC AMD UltraScale+™ Families AMD UltraScale™ Architecture AMD Zynq ™ 7000 SoC , 7 series FPGAs |
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Supported User Interfaces |
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Resources |
Performance and Resource Utilization web page |
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Provided with Core |
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Design Files |
Encrypted RTL |
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Example Design |
Not Provided |
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Test Bench |
Verilog |
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Constraints File |
XDC |
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Simulation Models |
Encrypted RTL, VHDL, or Verilog Structural |
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Supported Software Drivers |
Standalone |
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Design Entry Tools |
Vivado ™ Design Suite |
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Simulation |
For supported simulators, see the
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Synthesis Tools |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 54541 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete listing of supported devices, see the Vivado IP Catalog. 2. Refer to the Video IP: AXI Feature Adoption section of AXI Reference Guide [Ref 8] .
3.
For the supported versions of they tools, see the
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