AMD Adaptive Computing documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All AMD Versal ™ adaptive SoC design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:
• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware platform, creating PL kernels, subsystem functional simulation, and evaluating the AMD Vivado ™ timing, resource and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:
° Core Interfaces and Register Space
° Clocking
° Resets