Example Using the Default 720p Settings - 6.2 English

Video Timing Controller Product Guide (PG016)
Document ID
PG016
Release Date
2023-11-03
Version
6.2 English

Start with the default 720p settings without any fine timing adjustment settings:

Figure 4-4: Default/Constant Tab Settings

X-Ref Target - Figure 4-4

gui1.png

In simulation, look at the VTC output. Note that the pixel clock for 720p should be 74.5 MHz, equivalent to a period of 13.4 ns.

By default, the blanking signal rises at the same clock edge the last active video signal (of a frame) falls and falls at the same clock edge the first active video signal (of a frame) rises.

Figure 4-5: VTC Timing Waveform

X-Ref Target - Figure 4-5

gui2.png

Also by default, the vsync signals rises and falls at the same clock edge as a rising edge of the sixth rising edge of the hblank signal.

Figure 4-6: VTC Timing Waveform - vblank_out Zoomed In

X-Ref Target - Figure 4-6

gui3.png

Both behaviors are because only the Vertical timing in Lines count are configured, not in pixel count, defined in the video timing specifications.

But, for whatever reason, you might want to slightly change the configuration to move the Vertical blanking or Sync signals. Use the Horizontal Fine Adjustment Settings to do so.

Start by the blanking and use the following configuration:

Vblank start = 1285 and Vblank End = 1645

Figure 4-7: Default Constant Tab - Vblank Start/End

X-Ref Target - Figure 4-7

gui4.png

Now check the VTC outputs in simulation and regenerate the IP output products.

Notice that the blanking signal rises 67 ns after the active out signal falls. This correspond to 5 pixel clock periods. Taking the time from the last hblank signals of the active frame (indicating the last line), it corresponds to 1285 pixel clock periods (active size + 5).

Figure 4-8: VTC Timing Waveform - vblank_out

X-Ref Target - Figure 4-8

5.png

Notice that blanking signal falls 67 ns before the active out signal rises. This correspond to 5 pixel clock periods. Taking the time from the last hblank signals during the vertical blanking, it corresponds to 1645 pixel clock periods (horizontal frame size - 5).

Figure 4-9: VTC Timing Waveform - active_video_out

X-Ref Target - Figure 4-9

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Now change the Vsync start and End (0 and 1275):

Figure 4-10: Default Constant Tab - VSync Start/End

X-Ref Target - Figure 4-10

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Then check the output in simulation.

Notice that the vsync signal rises when the fifth falling edge of the hblank signal when the vertical blanking signals occur.

Figure 4-11: VTC Timing Waveform - vsync_out

X-Ref Target - Figure 4-11

8.png

And the vsync signal falls 5 clock cycles before the rising edge of a hblank .

Figure 4-12: VTC Timing Waveform - vsync_out Zoomed In

X-Ref Target - Figure 4-12

9.png

In summary, the Horizontal Fine adjustment allows you to move the Vertical timing signals in clock cycle precision while it is usually defined in Line precision.