The fsync_in Pin - 6.2 English

Video Timing Controller Product Guide (PG016)

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6.2 English

The fsync_in pin is an active-High input. The video timing generator is synchronized to the fsync_in input if used. The fsync_in should be driven High for only one clock cycle per frame. This resets all internal generator counters and starts the generated frame timing synchronized to this input. Internally, the fsync_in pin is logically "OR" combined with the internal frame sync det_fsync , produced by the detector. The internal frame sync det_fsync is generated by the video timing detector and can be used to synchronize the generator timing to the detector timing. The internal logic for this is show in This Figure . If the fsync_in input is used, then the detector must be disabled. Likewise, if the detector is used, then the fsync_in pin must be driven to '0'. The use of the external fsync_in pin and the detector can be changed at run-time but it is important that fsync_in and det_fsync are never asserted simultaneously.

Figure 2-4: Video Timing Controller Internal fsync Logic

X-Ref Target - Figure 2-4