|
Pin Name
|
Dir
|
Width
|
Description
|
|
AXI Write Address Channel Signals
(
1
)
|
|
s_axi_aclk
|
I
|
1
|
AXI4-Lite Clock
|
|
s_axi_aclken
|
I
|
1
|
AXI4-Lite active-High Clock Enable
|
|
s_axi_aresetn
|
I
|
1
|
AXI4-Lite active-Low Synchronous Reset
|
|
s_axi_awaddr
|
I
|
[(c_s_axi_addr_width-1):0]
|
AXI4-Lite Write Address Bus. The write address bus gives the address of the write transaction.
|
|
s_axi_awvalid
|
I
|
1
|
AXI4-Lite Write Address Channel Write Address Valid. This signal indicates that valid write address is available.
1 = Write address is valid.
0 = Write address is not valid.
|
|
s_axi_awready
|
O
|
1
|
AXI4-Lite Write Address Channel Write Address Ready. Indicates core is ready to accept the write address.
1 = Ready to accept address.
0 = Not ready to accept address.
|
|
AXI Write Data Channel Signals
(
1
)
|
|
s_axi_wdata
|
I
|
[(c_s_axi_data_width-1):0]
|
AXI4-Lite Write Data Bus.
|
|
s_axi_wstrb
|
I
|
[c_s_axi_data_width/8-1:0]
|
AXI4-Lite Write Strobes. This signal indicates which byte lanes to update in memory.
|
|
s_axi_wvalid
|
I
|
1
|
AXI4-Lite Write Data Channel Write Data Valid. This signal indicates that valid write data and strobes are available.
1 = Write data/strobes are valid.
0 = Write data/strobes are not valid.
|
|
s_axi_wready
|
O
|
1
|
AXI4-Lite Write Data Channel Write Data Ready. Indicates core is ready to accept the write data.
1 = Ready to accept data.
0 = Not ready to accept data.
|
|
s_axi_wready
|
O
|
1
|
AXI4-Lite Write Data Channel Write Data Ready. Indicates core is ready to accept the write data.
1 = Ready to accept data.
0 = Not ready to accept data.
|
|
AXI Write Response Channel Signals
(
1
)
|
|
s_axi_bresp
(
2
)
|
O
|
[1:0]
|
AXI4-Lite Write Response Channel. Indicates results of the write transfer.
00b = OKAY - Normal access has been successful.
01b = EXOKAY - Not supported.
10b = SLVERR - Error.
11b = DECERR - Not supported.
|
|
s_axi_bvalid
|
O
|
1
|
AXI4-Lite Write Response Channel Response Valid. Indicates response is valid.
1 = Response is valid.
0 = Response is not valid.
|
|
s_axi_bready
|
I
|
1
|
AXI4-Lite Write Response Channel Ready. Indicates Master is ready to receive response.
1 = Ready to receive response.
0 = Not ready to receive response.
|
|
AXI Read Address Channel Signals
(
1
)
|
|
s_axi_araddr
|
I
|
[(C_S_AXI_ADDR_WIDTH-1):0]
|
AXI4-Lite Read Address Bus. The read address bus gives the address of a read transaction.
|
|
s_axi_arvalid
|
I
|
1
|
AXI4-Lite Read Address Channel Read Address Valid.
1 = Read address is valid.
0 = Read address is not valid.
|
|
s_axi_arready
|
O
|
1
|
AXI4-Lite Read Address Channel Read Address Ready. Indicates core is ready to accept the read address.
1 = Ready to accept address.
0 = Not ready to accept address.
|
|
AXI Read Data Channel Signals
(
1
)
|
|
s_axi_rdata
|
O
|
[(C_S_AXI_DATA_WIDTH-1):0]
|
AXI4-Lite Read Data Bus.
|
|
s_axi_rresp
(
2
)
|
O
|
[1:0]
|
AXI4-Lite Read Response Channel Response. Indicates results of the read transfer.
00b = OKAY - Normal access has been successful.
01b = EXOKAY - Not supported.
10b = SLVERR - Error.
11b = DECERR - Not supported.
|
|
s_axi_rvalid
|
O
|
1
|
AXI4-Lite Read Data Channel Read Data Valid. This signal indicates that the required read data is available and the read transfer can complete.
1 = Read data is valid.
0 = Read data is not valid.
|
|
s_axi_rready
|
I
|
1
|
AXI4-Lite Read Data Channel Read Data Ready. Indicates master is ready to accept the read data.
1 = Ready to accept data.
0 = Not ready to accept data.
|
|
Notes:
1.
The function and timing of these signals are defined in the AMBA AXI Protocol Version: 2.0 Specification.
2.
For signals S_AXI_RRESP[1:0] and S_AXI_BRESP[1:0], the core does not generate the Decode Error ('11') response.
Other responses such as '00' (OKAY) and '10' (SLVERR) are generated by the core based upon certain conditions.
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