Stage 3: PL Kernel Analysis - 2022.1 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

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2022.1 English

The goal of this stage is to determine the exact PL kernel(s) causing a throughout drop.

Figure 1. PL Kernel Analysis

The sections below list the different techniques available in this stage.

Profiling Using PL Profile Monitors

You can insert PL profile monitors using the v++ link command. This allows you to monitor active, stalled cycles and bytes transferred on specific PL-AI Engine interfaces. This can be enabled along with event tracing in the AI Engine to minimize the build time. This will allow you to identify specific PL kernel(s) causing a performance drop. For more information on the option for adding PL profile monitors, see --profile Options in Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).

Replacing PL Kernels

You can replace each of the PL kernel that you suspect might be contributing a performance drop with non-throttling PL kernels. This allows you to determine if the PL kernel is responsible for the performance drop.

Inserting ILA(s) to Monitor Specific AXI Interfaces

You can insert one or more ILAs to monitor specific PL AXI interfaces to help identify exactly where and when a throughput drop occurs. It will also help you identify how frequently a throughput drop occurs. For details on the option to insert ILAs using the v++ command line, see Enabling Kernels for Debugging with Chipscope in Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).

Next Stage: After you determine the cause of throughput drop and fix the issue, proceed to stage 1 to rerun the design.