Hardware Profile and Debug Methodology - 2022.1 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

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2022.1 English

Designs running on Versal® AI Engine devices can target the AI Engine, PL, and Arm® host. To ensure a design targeting such multi-domain devices is functionally correct and meets the design performance specification, Xilinx® recommends a five-stage profile and debug methodology in hardware.

The stages are as follows:

  1. Design Execution and System Metrics
  2. System Profiling
  3. PL Kernel Analysis
  4. AI Engine Event Trace and Analysis
  5. Host Application Debug
Figure 1. Five Stages of Profile and Debug Methodology

The goal of each stage along with available tools and techniques are described below.