Targeting the DFX Platform

The Vitis DFX platform contains a static region and DFX regions.

Static Region: Harden block that is loaded in system booting. It is not able to be reconfigured in run-time.
DFX region: A reconfiguration partition (RP) that is implemented by the Vivado IP integrator block design container (BDC). A reconfiguration module (RM) is loaded into RP at run-time.

Xilinx provides a base DFX platform, xilinx_vck190_base_dfx_202210_1, which is a single RP DFX platform, meaning that it contains a static region and only one DFX region (or RM). The RM contains an AI Engine array and PL kernels. When loading, the entire AI Engine array and all PL kernels are loaded at one time. Following picture shows the block design (BD) of the base DFX platform.

Figure 1. Block Design of the Base DFX Platform

The static partition contains the following:

CIPS and PS NoC
Clock, Reset, Interrupt, and AXI interconnections
NoC Interface and DDR Memory Controller

The DFX region contains an AI Engine array and PL kernels that are linked together by the Vitis linker (v++ -l). The following picture shows an example of the DFX region generated by the Vitis linker.

Figure 2. Block Design of a DFX Region

The DFX region and static region interfaces include:

Clock and Reset
Inter-NoC Interface (INI) outputs to general memory
INI input from PS to control AI Engine
AXI Interface from PS to control PL kernels

The contains within the DFX region can include:

AI Engine
PL kernels
AXI-NoC IP
Clock and reset modules
AXI Interconnect module
ILA
FIFO, Data Width Converter (DWC) and CDC modules

When targeting a DFX platform, the aiecompiler, v++ compiler (v++ -c) and v++ linker (v++ -l) commands can be referred to in the base platform. The v++ packager (v++ -p) is different in the DFX platform than in the base platform. And v++ packager is different in hw and hw_emu modes in the DFX platform.

HW Deployment Flow

For a hw flow, the v++ packager for the DFX platform can be:

v++ -p -t hw -f xilinx_vck190_base_dfx_202210_1 
  --package.defer_aie_run \
  -o rm.xclbin \
  ${XSA} \
  libadf.a

v++ -p -t hw -f xilinx_vck190_base_dfx_202210_1 
  --package.rootfs ${ROOTFS} 
  --package.kernel_image ${IMAGE} \
  --package.boot_mode=sd \
  --package.image_format=ext4 \
  --package.sd_dir data \
  --package.sd_file ${HOST_EXE} \
  --package.sd_file rm.xclbin

Where,

The first v++ -p command generates an xclbin file that contains the RM PDI that will be loaded at run-time.
The second v++ -p command packages the RM xclbin file (rm.xclbin) into the SD card that can be read by the host program.

After Linux has started, type the following command at the prompt:

cd /run/media/mmcblk0p1
./host.exe rm.xclbin

Note: If the XRT detects that the same XCLBIN has been downloaded already, it will not download the XCLBIN again by default. Instead, it loads metadata from the xclbin file only.

To make sure XCLBIN is downloaded and the device is clean every time, set xrt.ini to enforce XCLBIN download to the device as follows:

Add following configuration to the xrt.ini file:
```
[Runtime]
force_program_xclbin=true
```
Place the file in the directory where the host program runs.

This ensures the XRT downloads the XCLBIN to device every time.

HW Emulation Deployment Flow

For hw_emu flow, the v++ packager command can be:

emconfigutil --platform xilinx_vck190_base_dfx_202210_1 --nd 1
v++ -p -t hw_emu -f xilinx_vck190_base_dfx_202210_1 \
  --package.defer_aie_run \
  --package.rootfs ${ROOTFS} \
  --package.kernel_image ${IMAGE} \
  --package.boot_mode=sd \
  --package.image_format=ext4 \
  --package.sd_dir data \
  --package.sd_file ${HOST_EXE} \
  --package.sd_file emconfig.json \
  -o rm.xclbin \
  ${XSA} \
  libadf.a

Launch the emulation with the following command:

./launch_hw_emu.sh

In QEMU, following commands can be run:

cd /run/media/mmcblk0p1
export XCL_EMULATION_MODE=hw_emu
./host.exe rm.xclbin rm.xclbin

Note: In hw_emu mode, you can download XCLBIN only once. The RM cannot be reloaded.

Targeting the DFX Platform - 2022.1 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

HW Deployment Flow

HW Emulation Deployment Flow