Packet Switching and the AI Engine Simulator - 2022.1 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

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2022.1 English

Explicit packet switching is supported by the AI Engine simulator. Consider the example of the previous graph that expects packet switched data from the PL; the data is split inside the AI Engine and sent to four AI Engine kernels. On the output side the four kernel outputs are merged into one output stream to the PL.

The input data file from the PL contains all the packet switched data from the PL, for the four AI Engine kernels in the previous example. It contains the data for different kernels, packet by packet. Each packet of data is for one window input for an AI Engine kernel. The data format is as follows.

Here, 2415853568 is 0x8fff0000 in hex format. The five least significant bits are the packet ID, 0 in this case. The last data in the packet has the keyword TLAST, which denotes the last data for the window input for the kernel.
Note: Integer values only are accepted as a packet header ID for the PL packet inputs to the AI Engine simulator.

You can construct the header for each packet manually, or write helper functions to generate the header. The AI Engine compiler generates a packet switching report file Work/reports/packet_switching_report.json that lists the packet IDs used in the graph. In addition it also generates Work/temp/packet_ids_c.h and Work/temp/packet_ids_v.h header files that can be included in your C or Verilog kernel code.