The AI Engine clock can run at up to 1 GHz for -1L speed grade devices, or higher, for -2 and -3 speed grade devices. The default width of a stream channel is 32 bits. Because this frequency is higher than the PL clock frequency, it is always necessary to perform a clock domain crossing to the PL region, for example, to either one-half or a quarter of the AI Engine clock frequency.
Recommended: Though
not required, Xilinx recommends running the PL
kernel with a frequency where the AI Engine frequency is an integer multiple of the PL kernel frequency.
For C++ HLS PL kernels, choose an appropriate target frequency depending on
the complexity of the algorithm implemented. The --hls.clock option can be used in the Vitis compiler when compiling HLS C/C++ into Xilinx object (XO) files.