The Hierarchy view uses the following icons:
- Top module
- Missing File/Module/Instance
- Out-of-Context Module
- Global Include File
- Verilog Header File
- Verilog File
- SystemVerilog File
- VHDL File
- Constraint File
- Tcl File
- IP
- Locked IP
- Block Design
- Design Checkpoint
- Netlist
- Hidden Instantiation
- Report
Tip: When a file, module
definition, or instantiation of a module is missing in the design hierarchy, the
Show only missing sources button is
enabled in the Sources window local
toolbar.