Parameterized Macro: Bus Synchronizer with Full Handshake
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_CDC
Introduction
This macro uses a handshake signaling to transfer an input bus from the source clock domain to the destination clock domain. One example of when this macro should be used is when the data being transferred is not compatible with the XPM_CDC_GRAY macro that uses Gray encoding.
For this macro to function correctly, a full handshake—an acknowledgement that the data transfer was received and a resetting of the handshake signals—must be completed before another data transfer is initiated.
You can define the number of register stages used in the synchronizers to transfer the handshake signals between the clock domains individually. You can also include internal handshake logic to acknowledge the receipt of data on the destination clock domain. When this feature is enabled, the output (dest_out) must be consumed immediately when the data valid (dest_req) is asserted.
You should run report_cdc to make sure the CDC structure is identified and that no critical warnings are generated, and also verify that dest_clk can sample src_in[n:0] two or more times.
External Handshake
Internal Handshake
Port Descriptions
Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
dest_ack | Input | 1 | dest_clk | LEVEL_HIGH | 0 |
Destination logic acknowledgement if DEST_EXT_HSK = 1. Unused when DEST_EXT_HSK = 0. Asserting this signal indicates that data on dest_out has been captured by the destination logic. This signal should be deasserted once dest_req is deasserted, completing the handshake on the destination clock domain and indicating that the destination logic is ready for a new data transfer. |
dest_clk | Input | 1 | NA | EDGE_RISING | Active | Destination clock. |
dest_out | Output | WIDTH | dest_clk | NA | Active | Input bus (src_in) synchronized to destination clock domain. This output is registered. |
dest_req | Output | 1 | dest_clk | LEVEL_HIGH | Active |
Assertion of this signal indicates that new dest_out data has been received and is ready to be used or captured by the destination logic.
This output is registered. |
src_clk | Input | 1 | NA | EDGE_RISING | Active | Source clock. |
src_in | Input | WIDTH | src_clk | NA | Active | Input bus that will be synchronized to the destination clock domain. |
src_rcv | Output | 1 | src_clk | LEVEL_HIGH | Active |
Acknowledgement from destination logic that src_in has been received. This signal will be deasserted once destination handshake has fully completed, thus completing a full data transfer. This output is registered. |
src_send | Input | 1 | src_clk | LEVEL_HIGH | Active | Assertion of this signal allows the src_in bus to be synchronized to the destination clock domain.
|
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DEST_EXT_HSK | DECIMAL | 1, 0 | 1 |
0- An internal handshake will be implemented in the macro to acknowledge receipt of data on the destination clock domain. When using this option, the valid dest_out output must be consumed immediately to avoid any data loss. 1- External handshake logic must be implemented by the user to acknowledge receipt of data on the destination clock domain. |
DEST_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages used to synchronize signal in the destination clock domain. |
INIT_SYNC_FF | DECIMAL | 0, 1 | 0 |
0- Disable behavioral simulation initialization value(s) on synchronization registers. 1- Enable behavioral simulation initialization value(s) on synchronization registers. |
SIM_ASSERT_CHK | DECIMAL | 0, 1 | 0 |
0- Disable simulation message reporting. Messages related to potential misuse will not be reported. 1- Enable simulation message reporting. Messages related to potential misuse will be reported. |
SRC_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages used to synchronize signal in the source clock domain. |
WIDTH | DECIMAL | 1 to 1024 | 1 | Width of bus that will be synchronized to destination clock domain. |
VHDL Instantiation Template
Library xpm;
use xpm.vcomponents.all;
-- xpm_cdc_handshake: Bus Synchronizer with Full Handshake
-- Xilinx Parameterized Macro, version 2021.1
xpm_cdc_handshake_inst : xpm_cdc_handshake
generic map (
DEST_EXT_HSK => 1, -- DECIMAL; 0=internal handshake, 1=external handshake
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_SYNC_FF => 4, -- DECIMAL; range: 2-10
WIDTH => 1 -- DECIMAL; range: 1-1024
)
port map (
dest_out => dest_out, -- WIDTH-bit output: Input bus (src_in) synchronized to destination clock domain.
-- This output is registered.
dest_req => dest_req, -- 1-bit output: Assertion of this signal indicates that new dest_out data has been
-- received and is ready to be used or captured by the destination logic. When
-- DEST_EXT_HSK = 1, this signal will deassert once the source handshake
-- acknowledges that the destination clock domain has received the transferred
-- data. When DEST_EXT_HSK = 0, this signal asserts for one clock period when
-- dest_out bus is valid. This output is registered.
src_rcv => src_rcv, -- 1-bit output: Acknowledgement from destination logic that src_in has been
-- received. This signal will be deasserted once destination handshake has fully
-- completed, thus completing a full data transfer. This output is registered.
dest_ack => dest_ack, -- 1-bit input: optional; required when DEST_EXT_HSK = 1
dest_clk => dest_clk, -- 1-bit input: Destination clock.
src_clk => src_clk, -- 1-bit input: Source clock.
src_in => src_in, -- WIDTH-bit input: Input bus that will be synchronized to the destination clock
-- domain.
src_send => src_send -- 1-bit input: Assertion of this signal allows the src_in bus to be synchronized
-- to the destination clock domain. This signal should only be asserted when
-- src_rcv is deasserted, indicating that the previous data transfer is complete.
-- This signal should only be deasserted once src_rcv is asserted, acknowledging
-- that the src_in has been received by the destination logic.
);
-- End of xpm_cdc_handshake_inst instantiation
Verilog Instantiation Template
// xpm_cdc_handshake: Bus Synchronizer with Full Handshake
// Xilinx Parameterized Macro, version 2021.1
xpm_cdc_handshake #(
.DEST_EXT_HSK(1), // DECIMAL; 0=internal handshake, 1=external handshake
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.SRC_SYNC_FF(4), // DECIMAL; range: 2-10
.WIDTH(1) // DECIMAL; range: 1-1024
)
xpm_cdc_handshake_inst (
.dest_out(dest_out), // WIDTH-bit output: Input bus (src_in) synchronized to destination clock domain.
// This output is registered.
.dest_req(dest_req), // 1-bit output: Assertion of this signal indicates that new dest_out data has been
// received and is ready to be used or captured by the destination logic. When
// DEST_EXT_HSK = 1, this signal will deassert once the source handshake
// acknowledges that the destination clock domain has received the transferred data.
// When DEST_EXT_HSK = 0, this signal asserts for one clock period when dest_out bus
// is valid. This output is registered.
.src_rcv(src_rcv), // 1-bit output: Acknowledgement from destination logic that src_in has been
// received. This signal will be deasserted once destination handshake has fully
// completed, thus completing a full data transfer. This output is registered.
.dest_ack(dest_ack), // 1-bit input: optional; required when DEST_EXT_HSK = 1
.dest_clk(dest_clk), // 1-bit input: Destination clock.
.src_clk(src_clk), // 1-bit input: Source clock.
.src_in(src_in), // WIDTH-bit input: Input bus that will be synchronized to the destination clock
// domain.
.src_send(src_send) // 1-bit input: Assertion of this signal allows the src_in bus to be synchronized to
// the destination clock domain. This signal should only be asserted when src_rcv is
// deasserted, indicating that the previous data transfer is complete. This signal
// should only be deasserted once src_rcv is asserted, acknowledging that the src_in
// has been received by the destination logic.
);
// End of xpm_cdc_handshake_inst instantiation