BUFGMUX_CTRL - 2021.1 English

Primitive: 2-to-1 General Clock MUX Buffer

PRIMITIVE_GROUP: CLOCK
PRIMITIVE_SUBGROUP: MUX

Introduction

This design element is a general clock buffer with two clock inputs, one clock output, and a select line used to cleanly select between one of two clocks driving the clocking resources. This component is based on BUFGCTRL, with some pins connected to logic High or Low. This element uses the S pin as the select pin for the 2-to-1 MUX. S can switch anytime without causing a glitch on the output clock of the buffer.

Port Descriptions

Port	Direction	Width	Function
I0	Input	1	Clock buffer input. This input is reflected on the output O when the S input is zero.
I1	Input	1	Clock buffer input. This input is reflected on the output O when the S input is one.
O	Output	1	Clock buffer output.
S	Input	1	Clock buffer select input. When Low, selects the I0 input and when High, selects the I1 input.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- BUFGMUX_CTRL: 2-to-1 General Clock MUX Buffer
--               Versal Prime series
-- Xilinx HDL Language Template, version 2021.1

BUFGMUX_CTRL_inst : BUFGMUX_CTRL
port map (
   O => O,   -- 1-bit output: Clock output
   I0 => I0, -- 1-bit input: Clock input (S=0)
   I1 => I1, -- 1-bit input: Clock input (S=1)
   S => S    -- 1-bit input: Clock select
);

-- End of BUFGMUX_CTRL_inst instantiation

Verilog Instantiation Template


// BUFGMUX_CTRL: 2-to-1 General Clock MUX Buffer
//               Versal Prime series
// Xilinx HDL Language Template, version 2021.1

BUFGMUX_CTRL BUFGMUX_CTRL_inst (
   .O(O),   // 1-bit output: Clock output
   .I0(I0), // 1-bit input: Clock input (S=0)
   .I1(I1), // 1-bit input: Clock input (S=1)
   .S(S)    // 1-bit input: Clock select
);

// End of BUFGMUX_CTRL_inst instantiation

Related Information

Versal ACAP Clocking Resources Architecture Manual (AM003)