Primitive: 6-Bit Look-Up Table with Carry
- PRIMITIVE_GROUP: CLB
- PRIMITIVE_SUBGROUP: LUT
Introduction
6-Bit look-up Table with carry.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I0 | Input | 1 | LUT input |
| I1 | Input | 1 | LUT input |
| I2 | Input | 1 | LUT input |
| I3 | Input | 1 | LUT input |
| I4 | Input | 1 | LUT input |
| O51 | Output | 1 | LUT output |
| O52 | Output | 1 | LUT output |
| PROP | Output | 1 | LUT output |
Design Entry Method
| Instantiation | Yes |
| Inference | Recommended |
| IP and IP Integrator Catalog | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| INIT | HEX | Any 64-bit HEX value | All zeroes | Specifies the logical expression of this element. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT6CY: 6-Bit Look-Up Table with Carry
-- Versal Prime series
-- Xilinx HDL Language Template, version 2021.1
LUT6CY_inst : LUT6CY
generic map (
INIT => X"0000000000000000" -- Logic function
)
port map (
O51 => O51, -- 1-bit output: LUT
O52 => O52, -- 1-bit output: LUT
PROP => PROP, -- 1-bit output: LUT
I0 => I0, -- 1-bit input: LUT
I1 => I1, -- 1-bit input: LUT
I2 => I2, -- 1-bit input: LUT
I3 => I3, -- 1-bit input: LUT
I4 => I4 -- 1-bit input: LUT
);
-- End of LUT6CY_inst instantiation
Verilog Instantiation Template
// LUT6CY: 6-Bit Look-Up Table with Carry
// Versal Prime series
// Xilinx HDL Language Template, version 2021.1
LUT6CY #(
.INIT(64'h0000000000000000) // Logic function
)
LUT6CY_inst (
.O51(O51), // 1-bit output: LUT
.O52(O52), // 1-bit output: LUT
.PROP(PROP), // 1-bit output: LUT
.I0(I0), // 1-bit input: LUT
.I1(I1), // 1-bit input: LUT
.I2(I2), // 1-bit input: LUT
.I3(I3), // 1-bit input: LUT
.I4(I4) // 1-bit input: LUT
);
// End of LUT6CY_inst instantiation
Related Information
- Versal ACAP Configurable Logic Block Architecture Manual (AM005)